seveibar/am3352-dev-board
A 324-ball TI AM3352 ARM processor with DDR3, LCD, USB, Ethernet, storage, serial, analog, clock, reset, power, and JTAG interfaces, paired with configurable JST-GH board connectors and constrained PCB routing.
- Version
- 1.0.2
- License
- unset
- Stars
- 0
design/ddr-via-sensitivity.json
{
"circuitSha256": "8d59215bb549d92980a490503cea35851e98dfd8d36fde491ebdf81b3529f9ab",
"method": "Sensitivity only: equally spaced copper planes across 1.2 mm; for each two-via byte path on top plus one other layer add 2 * layer index * 1.2 / 7 mm. Not a specified fabrication stackup or electrical-delay simulation.",
"groups": [
{
"byte": 0,
"shortest": "DDR_DQS0",
"longest": "DDR_D3",
"illustrativeSkewMm": 1.7436767142857121,
"limitMm": 0.635,
"nets": {
"DDR_D0": {
"layer": "inner2",
"planarMm": 18.499992,
"illustrativeTotalMm": 19.185706285714286
},
"DDR_D1": {
"layer": "inner3",
"planarMm": 18.499967,
"illustrativeTotalMm": 19.52853842857143
},
"DDR_D2": {
"layer": "bottom",
"planarMm": 18.470563,
"illustrativeTotalMm": 20.870562999999997
},
"DDR_D3": {
"layer": "bottom",
"planarMm": 18.520671,
"illustrativeTotalMm": 20.920671
},
"DDR_D4": {
"layer": "inner3",
"planarMm": 18.5,
"illustrativeTotalMm": 19.52857142857143
},
"DDR_D5": {
"layer": "inner5",
"planarMm": 18.470679,
"illustrativeTotalMm": 20.184964714285716
},
"DDR_D6": {
"layer": "inner4",
"planarMm": 18.5,
"illustrativeTotalMm": 19.87142857142857
},
"DDR_D7": {
"layer": "inner5",
"planarMm": 18.52071,
"illustrativeTotalMm": 20.234995714285716
},
"DDR_DQM0": {
"layer": "inner4",
"planarMm": 18.499992,
"illustrativeTotalMm": 19.87142057142857
},
"DDR_DQS0": {
"layer": "inner2",
"planarMm": 18.49128,
"illustrativeTotalMm": 19.176994285714287
},
"DDR_DQSn0": {
"layer": "inner2",
"planarMm": 18.5,
"illustrativeTotalMm": 19.185714285714287
}
}
},
{
"byte": 1,
"shortest": "DDR_DQS1",
"longest": "DDR_D10",
"illustrativeSkewMm": 1.0785684285714279,
"limitMm": 0.635,
"nets": {
"DDR_D8": {
"layer": "inner2",
"planarMm": 12.09997,
"illustrativeTotalMm": 12.785684285714286
},
"DDR_D9": {
"layer": "inner3",
"planarMm": 12.099961,
"illustrativeTotalMm": 13.128532428571429
},
"DDR_D10": {
"layer": "inner5",
"planarMm": 12.120695,
"illustrativeTotalMm": 13.834980714285713
},
"DDR_D11": {
"layer": "inner5",
"planarMm": 12.070717,
"illustrativeTotalMm": 13.785002714285714
},
"DDR_D12": {
"layer": "inner5",
"planarMm": 12.1,
"illustrativeTotalMm": 13.814285714285713
},
"DDR_D13": {
"layer": "inner3",
"planarMm": 12.070722,
"illustrativeTotalMm": 13.099293428571428
},
"DDR_D14": {
"layer": "inner5",
"planarMm": 12.070726,
"illustrativeTotalMm": 13.785011714285714
},
"DDR_D15": {
"layer": "inner4",
"planarMm": 12.070679,
"illustrativeTotalMm": 13.442107571428572
},
"DDR_DQM1": {
"layer": "inner2",
"planarMm": 12.07071,
"illustrativeTotalMm": 12.756424285714285
},
"DDR_DQS1": {
"layer": "inner2",
"planarMm": 12.070698,
"illustrativeTotalMm": 12.756412285714285
},
"DDR_DQSn1": {
"layer": "inner2",
"planarMm": 12.099972,
"illustrativeTotalMm": 12.785686285714284
}
}
}
]
}