seveibar/am3352-dev-board

REBUILD.md

# AM3352 pad escape cleanup

Changed the local clone of seveibar/am3352-dev-board 1.0.1.

- Removed 32 vias that had no inter-layer connection: 429 → 397.
- Regularized 82 CPU/RAM escapes into direct 45-degree dogbones.
- Kept 34 constrained candidates unchanged rather than violating clearance or the tight length-preservation budget.
- Rebuilt all copper pours and refreshed the filled/capped-via manifest (29 sites).
- Used published @tscircuit/core 0.0.1936 and @tscircuit/checks 0.0.200; removed the temporary core tarball dependency.

Validation on the rebuilt circuit:

- 138 nets, zero incomplete nets, zero geometric clearance violations.
- All 11 planar DDR checks pass; byte skews are 0.050147 mm and 0.050016 mm against 0.635 mm limits.
- DQS0/DQS1/CK pair skews are 0.008720/0.029274/0.020684 mm against 0.127 mm limits.
- Typecheck, endpoint/via connectivity regression tests, and cleanup checks pass.
- Native DRC retains the two existing crystal-net length errors: RTC_XTALIN 11.95 mm and XTALOUT 15.54 mm against 10 mm limits. Therefore the strict build exits 1 while still generating the output files.

`before-*.png` and `after-*.png` show the same top-layer viewports. `after-cpu-detail.png` clearly shows a removed unused via and the regularized dogbones beneath it.

The source ZIP includes the modified saved copper, timing constraints, reports, cleanup/verification scripts, and dependency lockfile. Run `npm install`, `npm run build`, `npm run verify:ddr`, and `npm run verify:pad-escapes`. For the independent copper audit install requirements.txt and run `python3 scripts/audit-copper.py`.

The registry package has not been republished. DDR measurements are planar lengths; the separate checks fallback still uses a fixed via-length allowance.