seveibar/am3352-dev-board

PROGRAMMING.md

# Cables, boot and programming

The board exposes UART0 on **J_PROG**, a locking JST-GH 1.25 mm connector, and USB0 on **J_USB0**, the existing micro-USB B connector. UART0 is the console and ROM serial-boot interface. USB0 is the peripheral boot interface; a suitable SPL/U-Boot build can also provide USB recovery/update functions. This AM3352 board has no onboard flash: persistent software lives on microSD. Bootloader images must be built for this board's RAM, clocks and PMIC configuration; no tested firmware is supplied.

## UART programming cable

J_PROG uses **BM04B-GHS-TBT**, mating housing **GHR-04V-S** and **SSHL-002T-P0.2** contacts. The silkscreen dot marks pin 1. Signals are named from the board's perspective.

| Pin | Board signal | USB-to-UART adapter connection |
|---|---|---|
| 1 | GND | Ground |
| 2 | UART0_TXD | Adapter RX |
| 3 | UART0_RXD | Adapter TX, 3.3 V logic |
| 4 | V3V3 | Target voltage reference; leave open unless the adapter requires a reference input |

Power the board through **J_PWR with 5 V**. The programming connector's pin 4 is the board's 3.3 V rail, not a 5 V input. Use a 3.3 V logic UART adapter, not an RS-232 interface. J_UART exposes the same UART for an ordinary header cable.

For initial bring-up, prepare a microSD with the board-specific SPL/U-Boot and use J_PROG for the console. For ROM serial loading, select a SYSBOOT device order that includes UART0, power-cycle, and use an AM335x-compatible serial boot loader to transfer the matching SPL and subsequent images. A terminal alone does not program the board.

## USB boot and recovery

Connect the host to **J_USB0** and supply 5 V separately at J_PWR. This revision's USB VBUS is sensed by the SoC; it does not power the board. Select a SYSBOOT device order containing USB0 before power-on. The AM335x ROM USB boot path uses a host-assisted boot protocol, not a USB mass-storage drag-and-drop programmer. Booting a prepared microSD and running a board-specific U-Boot build with USB DFU support is another possible recovery path.

J_BOOT0 through J_BOOT15 select the SYSBOOT levels: shunt 1–2 for high, 2–3 for low. Fit one shunt per selector. Select the complete 16-bit value using the AM335x TRM, including the 24 MHz oscillator encoding; this project does not prescribe an unverified shunt pattern. Re-sample the settings with a power cycle.

## Peripheral cable pinouts

| Connector | Header / mating housing | Pins 1 onward |
|---|---|---|
| J_SPI | BM06B-GHS-TBT / GHR-06V-S | GND, V3V3, SPI0_SCLK, SPI0_D0, SPI0_D1, SPI0_CS0 |
| J_I2C | BM04B-GHS-TBT / GHR-04V-S | GND, V3V3, I2C0_SDA, I2C0_SCL |

With SPI configured for D0 input and D1 output, D0 is MISO and D1 is MOSI. All cable interfaces use 3.3 V logic. J_I2C shares I2C0 with the PMIC and the existing GPIO header; onboard 4.7 kΩ pullups are already fitted. These are the same SPI/I²C buses exposed on J_GPIO, not additional independent controllers.

Sources: [TI boot process](https://e2echina.ti.com/cfs-file/__key/communityserver-discussions-components-files/120/The-Boot-Process.pdf), [TI USB ROM boot discussion](https://e2e.ti.com/support/processors-group/processors/f/processors-forum/167540/boot-using-usb-interface-for-flash-programming), [AM335x TRM](https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf), [JST GH mechanical drawings](https://www.jst-mfg.com/product/pdf/eng/eGH.pdf).

## What the SYSBOOT headers do

J_BOOT0–J_BOOT15 are startup configuration straps, not a debug interface. The AM3352 samples their levels on the rising edge of PWRONRSTn. The bits select the ROM boot-device search order, oscillator frequency, and options for particular boot interfaces. For example, SYSBOOT[15:14] selects the oscillator frequency; this board uses 24 MHz. Most upper/interface settings normally stay fixed while only the boot-device selection changes for recovery.

Each three-pin selector connects its middle pin through a 100 kΩ resistor to the corresponding LCD_DATA/SYSBOOT ball. A shunt on pins 1–2 selects 3.3 V (high); pins 2–3 selects ground (low). Use one shunt per selector and power-cycle after changing the settings. These headers do not carry a debugger protocol or program memory. J_JTAG is the debug interface; J_PROG provides the UART console/ROM-loading connection.

Exposing all sixteen bits is useful during initial bring-up, but is more configurable than a fixed-purpose board needs. A later hardware revision can hard-strap the fixed settings and retain a few boot-mode selectors.

Reference: [TI AM335x TRM, SYSBOOT configuration and ROM boot](https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf).