seveibar/am3352-dev-board

DDR-SKEW.md

# DDR length matching

**PCB centerline matching: PASS.** Measured from the compiled circuit, CPU ball center to RAM ball center. The route targets are 18.50 mm for byte 0, 12.10 mm for byte 1, and 35.02 mm for address/control and CK. Each byte includes its eight DQ signals, DM, and both DQS conductors.

| Group | Measured skew (mm) | Maximum (mm) | Result |
|---|---:|---:|---|
| Byte 0: DQ + DM | 0.050147 | 0.635 | PASS |
| Byte 0: DQ + DM + DQS envelope | 0.050147 | 0.635 | PASS |
| DQS0 differential pair | 0.008720 | 0.127 | PASS |
| Byte 1: DQ + DM | 0.050016 | 0.635 | PASS |
| Byte 1: DQ + DM + DQS envelope | 0.050016 | 0.635 | PASS |
| DQS1 differential pair | 0.029274 | 0.127 | PASS |
| CK differential pair | 0.020684 | 0.127 | PASS |
| Address/control + CK envelope | 0.050012 | 0.635 | PASS |

- Byte 0: placement-derived maximum length: longest 18.520710 mm; maximum 18.600277 mm. **PASS**.
- Byte 1: placement-derived maximum length: longest 12.120695 mm; maximum 12.200131 mm. **PASS**.
- Address/control + CK nominal length: 34.990699–35.040711 mm; allowed 33.750161–36.290161 mm. **PASS**.

The nominal limits use the longest actual CPU-to-RAM pin-pair Manhattan distance, rather than combining unrelated X/Y maxima. The address/control nominal adds 7.62 mm and permits ±1.27 mm. This is a single x16 RAM with direct point-to-point signal routes; there are no fly-by load branches. RESETn is listed below for reference and is excluded from the synchronous matching groups.

The independent Python validator reconstructs the routes from `pcb_trace` coordinates and source connectivity; it does not call `@tscircuit/checks` or read DRC results. It covers 47 DDR nets, including RESETn for reference. Its regression tests reject injected address skew, excessive absolute address length, and differential-pair skew.

**Overall DDR skew is not yet confirmed.** Byte signals use different layers, so equal via counts do not imply equal vertical travel. For example, DDR_D3 travels on bottom while DDR_DQS0 travels on inner2. The board specifies eight layers and 1.2 mm thickness but no physical layer depths or dielectric stackup. An illustrative equally spaced stackup gives approximately 1.744 mm byte-0 skew and 1.079 mm byte-1 skew in total geometric path lengths (including vertical travel), exceeding 0.635 mm. These are sensitivity estimates, not measured physical skew; see `design/ddr-via-sensitivity.json`. The fabrication stackup is needed to resolve this.

These are **geometric PCB lengths**, not electrical-delay or impedance signoff. The calculation excludes package delay, vertical via travel, dielectric differences between layers, and coupling. CK/DQS pair routing layers and via counts are reported explicitly. Fabricator stackup and signal-integrity review remain necessary before fabrication.

Constraints: [TI AM335x datasheet, Tables 7-68 and 7-69](https://www.ti.com/lit/ds/symlink/am3352.pdf). Recheck with `npm run verify:ddr`; it fails if any measured skew or placement-derived nominal limit fails. The JSX reference constraints are not used as evidence of compliance.

| Net | Pin-to-pin length (mm) | Path vias | Routing layers (mm) |
|---|---:|---:|---|
| DDR_A0 | 35.019994 | 2 | top: 0.9339, inner4: 34.0861 |
| DDR_A1 | 35.020000 | 0 | top: 35.0200 |
| DDR_A10 | 35.040475 | 2 | top: 0.9192, bottom: 34.1212 |
| DDR_A11 | 35.040648 | 2 | top: 0.9192, inner3: 34.1214 |
| DDR_A12 | 34.990714 | 2 | top: 0.9339, inner3: 34.0568 |
| DDR_A2 | 35.019946 | 2 | top: 0.9546, inner2: 34.0654 |
| DDR_A3 | 34.990716 | 2 | top: 0.9192, inner3: 34.0715 |
| DDR_A4 | 35.011222 | 2 | top: 0.9192, inner5: 34.0920 |
| DDR_A5 | 34.990727 | 3 | top: 0.9546, inner4: 29.8527, inner3: 4.1835 |
| DDR_A6 | 35.020000 | 2 | top: 0.9486, inner5: 34.0714 |
| DDR_A7 | 35.040622 | 2 | top: 0.9192, inner5: 34.1214 |
| DDR_A8 | 35.040680 | 2 | top: 0.9192, inner2: 34.1214 |
| DDR_A9 | 35.032113 | 2 | top: 0.9546, inner4: 34.0775 |
| DDR_BA0 | 35.040711 | 2 | top: 0.9341, inner3: 34.1066 |
| DDR_BA1 | 35.020000 | 0 | top: 35.0200 |
| DDR_BA2 | 35.032133 | 3 | top: 1.0195, inner5: 8.7462, bottom: 25.2665 |
| DDR_CASn | 35.020000 | 3 | top: 0.9693, bottom: 4.5157, inner3: 29.5350 |
| DDR_CK | 35.019970 | 2 | top: 0.9899, inner2: 34.0300 |
| DDR_CKE | 34.990711 | 2 | top: 0.9340, inner2: 34.0567 |
| DDR_CKn | 35.040654 | 2 | top: 0.9192, inner2: 34.1214 |
| DDR_CSn0 | 34.990714 | 4 | top: 0.9694, bottom: 29.6264, inner2: 4.3950 |
| DDR_D0 | 18.499992 | 2 | top: 0.9339, inner2: 17.5661 |
| DDR_D1 | 18.499967 | 2 | top: 0.9339, inner3: 17.5661 |
| DDR_D10 | 12.120695 | 2 | top: 0.9192, inner5: 11.2015 |
| DDR_D11 | 12.070717 | 2 | top: 0.9192, inner5: 11.1515 |
| DDR_D12 | 12.100000 | 2 | top: 0.9340, inner5: 11.1660 |
| DDR_D13 | 12.070722 | 2 | top: 0.9339, inner3: 11.1368 |
| DDR_D14 | 12.070726 | 2 | top: 0.9192, inner5: 11.1515 |
| DDR_D15 | 12.070679 | 2 | top: 0.9192, inner4: 11.1514 |
| DDR_D2 | 18.470563 | 2 | top: 0.9546, bottom: 17.5160 |
| DDR_D3 | 18.520671 | 2 | top: 0.9192, bottom: 17.6014 |
| DDR_D4 | 18.500000 | 2 | top: 0.9486, inner3: 17.5514 |
| DDR_D5 | 18.470679 | 2 | top: 0.9192, inner5: 17.5514 |
| DDR_D6 | 18.500000 | 2 | top: 0.9488, inner4: 17.5512 |
| DDR_D7 | 18.520710 | 2 | top: 0.9340, inner5: 17.5867 |
| DDR_D8 | 12.099970 | 2 | top: 0.9899, inner2: 11.1100 |
| DDR_D9 | 12.099961 | 2 | top: 0.9546, inner3: 11.1454 |
| DDR_DQM0 | 18.499992 | 2 | top: 0.9192, inner4: 17.5808 |
| DDR_DQM1 | 12.070710 | 2 | top: 0.9341, inner2: 11.1366 |
| DDR_DQS0 | 18.491280 | 2 | top: 0.9546, inner2: 17.5367 |
| DDR_DQS1 | 12.070698 | 2 | top: 0.9546, inner2: 11.1161 |
| DDR_DQSn0 | 18.500000 | 2 | top: 0.9841, inner2: 17.5159 |
| DDR_DQSn1 | 12.099972 | 2 | top: 0.9546, inner2: 11.1454 |
| DDR_ODT | 34.990699 | 4 | top: 0.9339, inner3: 6.6423, bottom: 20.8547, inner2: 6.5598 |
| DDR_RASn | 35.019999 | 3 | top: 4.5801, inner5: 14.2715, inner4: 16.1684 |
| DDR_RESETn | 24.053967 | 3 | top: 0.9192, inner4: 16.9869, inner5: 6.1479 |
| DDR_WEn | 35.032144 | 3 | top: 0.9546, inner2: 8.3248, inner5: 25.7528 |

Compiled circuit SHA-256: `8d59215bb549d92980a490503cea35851e98dfd8d36fde491ebdf81b3529f9ab`.