seveibar/am3352-dev-board-4layer-dogbone

scripts/update-validation-docs.py

"""Write human-readable status only from a validated native build and fresh reports."""
import json,hashlib
from pathlib import Path
c=json.load(open('dist/index/circuit.json'));sha=hashlib.sha256(Path('dist/index/circuit.json').read_bytes()).hexdigest();audit=json.load(open('design/copper-audit.json'));ddr=json.load(open('design/ddr-skew-check.json'));validation=json.load(open('design/validation.json'));filled=json.load(open('design/filled-vias.json'))
assert audit['circuitSha256']==ddr['circuitSha256']==sha
assert validation['fullyRouted'] and not audit['incompleteNets'] and not audit['clearanceViolations']
assert all(g['status']=='PASS' for g in ddr['groups'])
topology=json.load(open('design/ddr-topology.json'));assert topology['circuitSha256']==sha and topology['netsChecked']==46 and not topology['errors']
no_pad=json.load(open('design/no-via-in-pad.json'));assert no_pad['circuitSha256']==sha and no_pad['viaCount']>0 and not no_pad['violations']
via_count=len([e for e in c if e['type']=='pcb_via']);via_fill=len(filled['vias']);components=len([e for e in c if e['type']=='source_component']);skew=max(g.get('skewMm',0) for g in ddr['groups']);warnings={}
for e in c:
 if 'warning' in e['type']:warnings[e['type']]=warnings.get(e['type'],0)+1
Path('README.md').write_text('''# AM3352 four-layer dogbone board

Completed routed four-layer variant with no via-in-pad of `seveibar/am3352-dev-board@1.0.2`: 70 × 60 mm, 1.2 mm thick, with the original electrical netlist and DDR pin assignment. The oscillator parts were moved closer to their processor pins. C_U1_P14 was moved 2.61 mm and C_DDR7 was moved 0.54 mm; both were rotated 90 degrees to free dogbone escapes. C_U1_G5 moved 3.05 mm and rotated 90 degrees so R_VTP could sit on the underside next to the processor escape.

The native build passes with zero DRC errors. All 138 nets pass an independent physical copper connectivity and clearance audit. All 19 independent DDR length checks pass, including skew measured with the used vertical via spans. See [STATUS.md](STATUS.md), [DDR-SKEW.md](DDR-SKEW.md), and [ROUTING.md](ROUTING.md).

Assembly parts, manufacturer land patterns, supplier rotation mappings, and a separate manual-header BOM are included in [assembly/README.md](assembly/README.md). See [FABRICATION-REVIEW.md](FABRICATION-REVIEW.md) for the remaining electrical review.

The stack is top signals/components, inner1 ground, inner2 signals, bottom signals/components. Power rails are routed explicitly. The original eight-layer design is retained separately.

## Build and inspect

```sh
npm ci
python3 -m venv .venv
. .venv/bin/activate
pip install -r requirements.txt
npm run build:site
npm run audit:copper
npm run verify
npm run verify:layers
npm run verify:no-via-in-pad
npm run test:no-via-in-pad
npm run verify:ddr
npm run verify:ddr-topology
npm run test:ddr
npm run test:tooling
node scripts/export-assembly.mjs
python3 scripts/check-assembly.py
```

Serve `dist` with `python3 -m http.server 8000 --directory dist`, then open `http://localhost:8000/#file=index.circuit.tsx`. The generated site includes the TSX file, PCB views, schematic and 3D view.

## Scope of verification

This is a completed routed design, not fabrication or signal-integrity signoff. Its three signal layers plus one ground plane differ from TI's signal/ground/power/signal reference stack. Dielectrics, impedance, layer-dependent delay and package delay still require an engineering review. No via annulus overlaps an SMT pad on either face; all have at least 0.1 mm clearance in the independent audit. The generated filled/capped-via manifest is empty.

The pinned dependencies receive three reproducible connectivity fixes during `npm ci`: layer/net-aware endpoint inference, physical via contacts, and contacts through actual rendered pour polygons. Each has regression checks. No timing constraints or DRC errors are suppressed. Historical routing experiments under `routing-work` are excluded from the downloadable package.
''')
runtime={name:json.loads((Path('node_modules')/name/'package.json').read_text())['version'] for name in ['tscircuit','@tscircuit/core','@tscircuit/checks']}
Path('STATUS.md').write_text(f'''# Four-layer validation status

Circuit JSON SHA-256: `{sha}`.

- Runtime: tscircuit `{runtime['tscircuit']}`, core `{runtime['@tscircuit/core']}`, checks `{runtime['@tscircuit/checks']}`.
- Native `tsci build --site`: passed, zero DRC errors.
- Board: 70 × 60 × 1.2 mm; four copper layers.
- Components: {components}; through vias: {via_count}.
- Independent geometry: all {audit['nets']} nets connected; zero clearance violations at the audit's 3 µm comparison tolerance.
- DDR: all {len(ddr['groups'])} checks pass; largest measured group skew {skew:.6f} mm. Graph contacts use 1 µm resolution, so sub-micrometre numeric differences are not physical accuracy claims.
- Each matched DDR net uses three vias and 2.4 mm of vertical barrel travel.
- No-via-in-pad audit: passed, zero pad overlaps and 0.1 mm annulus clearance on both faces.
- Filled/capped via sites: {via_fill}; see the generated manifest.
- TypeScript, routing consistency, layer checks and validator regression tests pass.

Reports are tied to the compiled circuit hash. Regenerate them after any edit. Native advisory warnings remain: `{json.dumps(warnings,sort_keys=True)}`. These are not counted as DRC errors.

See README.md for the scope of verification and the remaining fabrication/SI review.
''')
targets=json.load(open('design/ddr-length-targets.json'));b0=targets['DDR_D0'];b1=targets['DDR_D8'];ac=targets['DDR_CK']
lines=['# Independent DDR length verification','','Measured directly from the final circuit JSON, without using the built-in DRC. Trace edges use unrounded centerline geometry and graph junctions use 1 µm resolution.','', 'All matched nets follow top → inner2 → bottom → top, or the reverse intermediate-layer order. Both paths traverse exactly twice the 1.2 mm board thickness. The resulting 2.4 mm vertical travel does not require an assumed inner-layer depth. The checker collapses graph-only intermediate nodes at each via before measuring used barrel travel.','', f'Planar targets are {b0:g} mm for byte 0, {b1:g} mm for byte 1, and {ac:g} mm for address/control/clock. Including barrels, these are {b0+2.4:g}, {b1+2.4:g} and {ac+2.4:g} mm. The placement-derived maximum checks below are explicitly planar; delay and impedance are not simulated.','', '| Check | Result | Skew / maximum (mm) | Limit (mm) |','|---|---|---:|---:|']
for g in ddr['groups']:
 value=g.get('skewMm',g.get('maximumLengthMm'));limit=g.get('limitMm',g.get('allowedMaximumMm'));lines.append(f"| {g['group']} | {g['status']} | {value:.6f} | {limit:.3f} |")
lines+=['','The address/control nominal planar interval is 33.75–36.29 mm. Source: [TI AM335x datasheet, Tables 7-68 and 7-69](https://www.ti.com/lit/ds/symlink/am3352.pdf).','', 'The pinned native checker uses 1.6 mm per via. Equal three-via counts mean this constant offset cancels in its skew checks; the independent barrel calculation above uses the actual 1.2 mm board thickness.','', '| Net | Planar length (mm) | Including used barrels (mm) | Vias on path |','|---|---:|---:|---:|']
for name,r in sorted(ddr['nets'].items()):lines.append(f"| {name} | {r['pathLengthMm']:.6f} | {r['lengthIncludingViasMm']:.6f} | {r['pathViaSites']} |")
lines+=['',f'Circuit JSON SHA-256: `{sha}`.',''];Path('DDR-SKEW.md').write_text('\n'.join(lines))
Path('ROUTING.md').write_text('''# Four-layer routing

The TSX custom router in `design/replay-router.ts` replays the saved, validated copper in `design/routed-copper.json`. It rejects changed endpoint placement and invalid layer names. tscircuit generates the ground pour and runs native DRC after replay.

The completed route uses top, inner2 and bottom for signals and power, with an explicit ground pour on inner1. The BGA pin mapping remains unchanged. DDR routes were generated with a negotiated-congestion maze router, then clearance-checked chamfered meanders were inserted to match their lengths. Three vias per matched net give equal used vertical travel. Native copper geometry, independent connectivity/clearance, planar lengths, and lengths including barrels are validated after the final build.

The existing USB pair skew constraint remains enforced. Local assembly-footprint clearance changes required a small USB route adjustment; the pair has not been rerouted together or qualified for impedance. The user deferred that review. DDR signal routes are unchanged by the assembly update.

L1–L3 and Y1/Y2 now use their manufacturer land patterns. The RTC crystal has an enforced top-copper body keepout; nearby capacitors and local copper were moved to provide assembly space. Supplier part numbers and placement rotations are recorded in the assembly directory.

The oscillator parts were placed closer to the CPU. Bottom capacitors C_U1_P14 and C_DDR7 moved 2.61 mm and 0.54 mm respectively; both rotated 90 degrees to free pad-safe escapes. C_U1_G5 moved 3.05 mm and rotated 90 degrees; its power pad remains 3.80 mm from its associated ball. R_VTP moved to the underside beside the processor dogbone. Both RTC oscillator nets stay on the top layer without vias. The reset pull resistor remains attached to its routed DDR reset net.

## Rebuild safeguards

- `verify.mjs` compares every saved route against the compiled route, rejects native errors, and requires a current passing independent physical audit.
- `audit-copper.py --strict` tests real pad, trace, via and rendered-pour geometry, including all layers of through vias.
- `check-four-layer-stack.py` rejects nonexistent layers.
- `check-ddr-skew.py --strict` measures all 47 DDR ball-to-ball paths and checks 19 length groups independently of native DRC.
- `test-ddr-validator.py` verifies rejection of skewed and uniformly overlong buses. `test-via-travel.py` covers barrel path accounting and unknown inner depths.
- Connectivity patches are installed reproducibly and tested against wrong-net, wrong-layer, via-isolation, pour-cutout and disconnected-pour cases.

Every SMT pad is included in the hard via exclusion mask, even when the pad and via share a net. `check-no-via-in-pad.py --strict` independently verifies annulus-to-pad clearance in the generated circuit, on both faces.

The chosen stack differs from TI's four-layer reference stack. Copper connectivity and length matching do not validate impedance, return-current paths, power integrity or DDR timing. See README.md.
''')
print('Updated README, status, routing and DDR measurements from',sha)