seveibar/am3352-dev-board-4layer-dogbone
Defines PCB footprints and pin mappings for a TI AM3352ZCZ100 processor, JST GH connectors, and assembly-part lookup helpers for capacitors, resistors, and headers.
- Version
- 0.1.5
- License
- unset
- Stars
- 0
scripts/test-ddr-topology.py
"""Ensure unintended same-net contacts cannot silently validate as length tuning."""
import json,os,subprocess,sys,tempfile
from pathlib import Path
base=[dict(type='source_net',name='DDR_D0',source_net_id='net'),dict(type='source_trace',source_trace_id='trace',connected_source_net_ids=['net'])]
def wire(points):return dict(type='pcb_trace',pcb_trace_id='wire',source_trace_id='trace',route=[dict(route_type='wire',x=x,y=y,layer='top',width=.1) for x,y in points])
def via(x,y):return dict(type='pcb_trace',pcb_trace_id='via',source_trace_id='trace',route=[dict(route_type='via',x=x,y=y,from_layer='top',to_layer='bottom',via_diameter=.3)])
with tempfile.TemporaryDirectory() as tmp:
inp=Path(tmp)/'circuit.json';out=Path(tmp)/'report.json'
def check(extra):
inp.write_text(json.dumps(base+extra));r=subprocess.run([sys.executable,'scripts/check-ddr-topology.py'],env={**os.environ,'AUDIT_CIRCUIT':str(inp),'DDR_TOPOLOGY_REPORT':str(out)},capture_output=True,text=True);assert r.returncode==0,r.stderr
return json.loads(out.read_text())['errors']
assert not check([wire([(-1,0),(1,0)]),via(-1,0),via(1,0)])
assert check([wire([(-1,0),(1,0)]),via(0,.1)])[0]['kind']=='unintended-via-contact-or-spacing'
assert not check([wire([(-1,0),(1,0)]),via(0,.4)])
assert check([wire([(-1,-1),(1,1),(-1,1),(1,-1)])])[0]['kind']=='self-intersection'
assert check([via(0,0),via(.3,0)])[0]['kind']=='via-to-via'
print('DDR topology regression passed: intended endpoints, unintended via contacts, crossing traces and via spacing')