seveibar/am3352-dev-board-4layer-dogbone

Defines PCB footprints and pin mappings for a TI AM3352ZCZ100 processor, JST GH connectors, and assembly-part lookup helpers for capacitors, resistors, and headers.

Version
0.1.5
License
unset
Stars
0

scripts/check-pour-connectivity.mjs

import assert from 'node:assert/strict'
import {PcbConnectivityMap} from 'circuit-json-to-connectivity-map'
const trace=(id,x,y)=>({type:'pcb_trace',pcb_trace_id:id,route:[{route_type:'wire',x,y,layer:'top',width:.1}]})
const via=(id,x,y)=>({type:'pcb_via',pcb_via_id:'v_'+id,pcb_trace_id:id,x,y,outer_diameter:.3,layers:['top','inner1','inner2','bottom']})
const ring=(a,b,c,d)=>({vertices:[{x:a,y:b},{x:c,y:b},{x:c,y:d},{x:a,y:d}]})
const pour=(id,outer,holes=[])=>({type:'pcb_copper_pour',pcb_copper_pour_id:id,layer:'inner1',shape:'brep',brep_shape:{outer_ring:outer,inner_rings:holes}})
const c=[trace('a',1,1),via('a',1,1),trace('b',4,4),via('b',4,4)]
const connected=(extra)=>new PcbConnectivityMap([...c,...extra]).getAllTracesConnectedToTrace('a').some(t=>t.pcb_trace_id==='b')
assert(connected([pour('p',ring(0,0,5,5))]))
assert(!connected([pour('p',ring(0,0,5,5),[ring(3,3,4.5,4.5)])]))
assert(!connected([pour('p1',ring(0,0,2,2)),pour('p2',ring(3,3,5,5))]))
assert(!connected([{...pour('p',ring(0,0,5,5)),layer:'inner9'}]))
console.log('Pour contacts: shared island, cutout, separate islands, and layer mismatch verified')