seveibar/am3352-dev-board-4layer-dogbone

Defines PCB footprints and pin mappings for a TI AM3352ZCZ100 processor, JST GH connectors, and assembly-part lookup helpers for capacitors, resistors, and headers.

Version
0.1.5
License
unset
Stars
0

scripts/check-endpoint-inference.mjs

import assert from 'node:assert/strict'
import { checkEachPcbPortConnectedToPcbTraces } from '@tscircuit/checks'
import { getFullConnectivityMapFromCircuitJson } from 'circuit-json-to-connectivity-map'
const base=[
 {type:'source_trace',source_trace_id:'source_trace_A',connected_source_port_ids:['source_port_A'],connected_source_net_ids:['source_net_A']},
 {type:'source_trace',source_trace_id:'source_trace_B',connected_source_port_ids:['source_port_B'],connected_source_net_ids:['source_net_B']},
 {type:'pcb_port',pcb_port_id:'pcb_port_A',source_port_id:'source_port_A',x:0,y:0,layers:['top']},
 {type:'pcb_port',pcb_port_id:'pcb_port_B',source_port_id:'source_port_B',x:3,y:0,layers:['top']},
 {type:'pcb_smtpad',pcb_smtpad_id:'pcb_smtpad_A',pcb_port_id:'pcb_port_A',shape:'rect',x:0,y:0,width:.6,height:.6,layer:'top'},
];
const trace=(source,layer)=>({type:'pcb_trace',pcb_trace_id:'pcb_trace_test',source_trace_id:source,route:[{route_type:'wire',x:0,y:0,width:.1,layer},{route_type:'wire',x:1,y:0,width:.1,layer}]});
for(const [source,layer,expected] of [['source_trace_A','top','pcb_port_A'],['source_trace_A','inner2',undefined],['source_trace_B','top',undefined],['source_trace_B','bottom',undefined]]){
 const t=trace(source,layer),c=structuredClone(base);c.push(t);checkEachPcbPortConnectedToPcbTraces(c);
 assert.equal(t.route[0].start_pcb_port_id,expected,source+' on '+layer);
 const m=getFullConnectivityMapFromCircuitJson(c);assert.notEqual(m.getNetConnectedToId('source_net_A'),m.getNetConnectedToId('source_net_B'));
}
console.log('Endpoint inference regression: correct-net surface contact, cross-layer isolation, and cross-net isolation passed');