seveibar/am3352-dev-board-4layer-dogbone

Defines PCB footprints and pin mappings for a TI AM3352ZCZ100 processor, JST GH connectors, and assembly-part lookup helpers for capacitors, resistors, and headers.

Version
0.1.5
License
unset
Stars
0

design/net-names.json

[
  "USB0_VBUS",
  "USB0_DM",
  "USB0_DP",
  "USB0_ID",
  "GND",
  "MMC0_DAT2",
  "SPI0_SCLK",
  "SPI0_D0",
  "I2C0_SDA",
  "MMC0_DAT3",
  "SPI0_CS0",
  "SPI0_D1",
  "I2C0_SCL",
  "UART0_TXD",
  "PWRONRSTn",
  "UART0_RXD",
  "EMU1",
  "EMU0",
  "V1V8",
  "V3V3",
  "VDD_MPU",
  "TCK",
  "TDO",
  "TDI",
  "TMS",
  "CAP_VDD_SRAM_MPU",
  "WARMRSTn",
  "TRSTn",
  "CAP_VBB_MPU",
  "CAP_VDD_SRAM_CORE",
  "RTC_1V8",
  "VDD_CORE",
  "RTC_XTALIN",
  "PMIC_POWER_EN",
  "CAP_VDD_RTC",
  "RTC_RESETn",
  "DDR_A6",
  "DDR_1V5",
  "RTC_XTALOUT",
  "DDR_BA0",
  "DDR_A8",
  "DDR_A2",
  "DDR_A10",
  "DDR_BA2",
  "DDR_A3",
  "DDR_A12",
  "DDR_A0",
  "DDR_WEn",
  "DDR_A4",
  "DDR_CK",
  "DDR_A7",
  "DDR_A11",
  "DDR_A5",
  "DDR_A9",
  "DDR_CKn",
  "DDR_BA1",
  "DDR_CASn",
  "MMC0_CMD",
  "MMC0_CLK",
  "MMC0_DAT0",
  "MMC0_DAT1",
  "DDR_RASn",
  "DDR_VREF",
  "DDR_D12",
  "DDR_D14",
  "DDR_D1",
  "DDR_CKE",
  "DDR_VTP",
  "DDR_D11",
  "DDR_D13",
  "DDR_D0",
  "DDR_RESETn",
  "DDR_CSn0",
  "DDR_DQM1",
  "DDR_D10",
  "DDR_DQSn1",
  "DDR_DQM0",
  "DDR_ODT",
  "DDR_A1",
  "DDR_D8",
  "DDR_D9",
  "DDR_DQS1",
  "DDR_D15",
  "A3V3",
  "XTALOUT",
  "XTALIN",
  "LCD_DATA15",
  "DDR_D5",
  "DDR_D7",
  "LCD_DATA3",
  "LCD_DATA7",
  "LCD_DATA11",
  "LCD_DATA14",
  "DDR_D4",
  "DDR_D6",
  "LCD_DATA2",
  "LCD_DATA6",
  "LCD_DATA10",
  "LCD_DATA13",
  "DDR_D3",
  "DDR_DQSn0",
  "LCD_DATA1",
  "LCD_DATA5",
  "LCD_DATA9",
  "LCD_DATA12",
  "DDR_D2",
  "DDR_DQS0",
  "LCD_DATA0",
  "LCD_DATA4",
  "LCD_DATA8",
  "VIN_5V",
  "SYS_5V",
  "PMIC_TS",
  "PMIC_INT_LDO",
  "PMIC_BYPASS",
  "PMIC_PB",
  "DDR_ZQ",
  "SD_CD",
  "SW1",
  "SW2",
  "SW3",
  "BOOT_SEL0",
  "BOOT_SEL1",
  "BOOT_SEL2",
  "BOOT_SEL3",
  "BOOT_SEL4",
  "BOOT_SEL5",
  "BOOT_SEL6",
  "BOOT_SEL7",
  "BOOT_SEL8",
  "BOOT_SEL9",
  "BOOT_SEL10",
  "BOOT_SEL11",
  "BOOT_SEL12",
  "BOOT_SEL13",
  "BOOT_SEL14",
  "BOOT_SEL15"
]