seveibar/am3352-dev-board-4layer-dogbone

Defines PCB footprints and pin mappings for a TI AM3352ZCZ100 processor, JST GH connectors, and assembly-part lookup helpers for capacitors, resistors, and headers.

Version
0.1.5
License
unset
Stars
0

design/ddr-length-targets.json

{
  "DDR_D0": 18.18,
  "DDR_D1": 18.18,
  "DDR_D2": 18.18,
  "DDR_D3": 18.18,
  "DDR_D4": 18.18,
  "DDR_D5": 18.18,
  "DDR_D6": 18.18,
  "DDR_D7": 18.18,
  "DDR_DQM0": 18.18,
  "DDR_DQS0": 18.18,
  "DDR_DQSn0": 18.18,
  "DDR_D8": 12.195,
  "DDR_D9": 12.195,
  "DDR_D10": 12.195,
  "DDR_D11": 12.195,
  "DDR_D12": 12.195,
  "DDR_D13": 12.195,
  "DDR_D14": 12.195,
  "DDR_D15": 12.195,
  "DDR_DQM1": 12.195,
  "DDR_DQS1": 12.195,
  "DDR_DQSn1": 12.195,
  "DDR_A6": 35.02,
  "DDR_BA0": 35.02,
  "DDR_A8": 35.02,
  "DDR_A2": 35.02,
  "DDR_A10": 35.02,
  "DDR_BA2": 35.02,
  "DDR_A3": 35.02,
  "DDR_A12": 35.02,
  "DDR_A0": 35.02,
  "DDR_WEn": 35.02,
  "DDR_A4": 35.02,
  "DDR_CK": 35.02,
  "DDR_A7": 35.02,
  "DDR_A11": 35.02,
  "DDR_A5": 35.02,
  "DDR_A9": 35.02,
  "DDR_CKn": 35.02,
  "DDR_BA1": 35.02,
  "DDR_CASn": 35.02,
  "DDR_RASn": 35.02,
  "DDR_CKE": 35.02,
  "DDR_CSn0": 35.02,
  "DDR_ODT": 35.02,
  "DDR_A1": 35.02
}