seveibar/am3352-dev-board-4layer-dogbone

assembly/README.md

# Assembly files

The assembly data is generated from the locally validated circuit, with its SHA-256 recorded in `orientation-audit.json` and `../design/assembly-check.json`. These files do not release the unresolved DDR stackup or power layout for fabrication; see `../FABRICATION-REVIEW.md`.

- `jlcpcb-bom.csv`: 163 SMT placements grouped by LCSC part number.
- `jlcpcb-cpl.csv`: those same 163 references, in millimetres, with top/bottom side and supplier-relative rotation.
- `manual-assembly.csv`: 21 through-hole headers, installed after SMT, plus 16 boot-strap shunts as loose accessories. Select the tested boot settings during bring-up; the shunts are not SMT placements.
- `top.svg` / `bottom.svg`: separate assembly views. The bottom view is shown through the board so its coordinates match the CPL.
- `orientation-audit.json`: board hash, all placement coordinates, and the authored/supplier pin-1 mappings. `TP_PB` is bare board copper, excluded from both BOMs.

All 184 populated board components have manufacturer part numbers. All 163 SMT components have JLCPCB codes. The 26 supplier orientation references and exact imported footprints are cached under `../design/assembly-supplier-footprints` and `../design/assembly-supplier-imports`; the importer commands and lookup date are in `../design/assembly-orientations.json`. The placement exporter requires resolved supplier rotations and rejects a board with native errors. The LED source uses supplier pin numbering (pin 1 cathode, pin 2 anode); its 180° rotation preserves the routed pad connections without an export-only polarity override. Passive 180° equivalence does not apply to that LED.

## Corrected mechanical details

| References | Selected part | Land pattern / mechanical basis |
|---|---|---|
| L1–L3 | Murata DFE201612E-2R2M=P2 | Two 0.8 × 1.8 mm lands, centres ±0.8 mm; 2.9 × 2.3 mm courtyard |
| Y1 | Abracon ABM3-24.000MHZ-D2Y-T | Two 1.9 × 2.4 mm lands, centres ±2.05 mm |
| Y2 | Epson Q13FC13500004 (FC-135) | Two 1.0 × 1.8 mm lands, centres ±1.25 mm; no top copper in the 1.5 × 1.8 mm space between lands |
| U1 | AM3352BZCZ100 | Added 16 × 16 mm courtyard around the 15 mm package |
| J_SPI/J_I2C/J_PROG | JST GH top-entry | Specified insertion direction; supplier pin-1 frames checked |
| J_BOOT0–15 | Harwin M50-3530342 | 1.27 mm pitch, 0.65 mm finished holes for 0.4 mm square tails; 3.81 × 2.10 mm nominal housing. Courtyard displays nominal housing +0.10 mm per edge. Maximum 4.31 × 2.35 mm housing envelope is independently checked against nearby parts. |
| Remaining headers | Samtec TSW, exact variants in manual BOM | 2.54 mm pitch; single row except 2×7 JTAG |

The RTC crystal and two nearby capacitors were repositioned to fit the actual package and copper keepout. Local routes and pad-adjacent vias were repaired. All DDR signal routes were retained. Both RTC oscillator nets remain on top without vias.

Manufacturer references: [Murata O05E land-pattern catalogue, printed page 139](https://www.tti.com/content/dam/ttiinc/manufacturers/murata/doc/murata-chip-coil-inductors-product-catalog.pdf), [Abracon ABM3 drawing](https://abracon.com/Resonators/ABM3.pdf), [Epson FC-135 application sheet, page 4](https://download.epsondevice.com/td/pdf/app/FC-135_en.pdf), [Harwin M50-3530342 drawing and specifications](https://www.harwin.com/products/M50-3530342), [Harwin boot shunt](https://www.harwin.com/products/M50-1900005), [Samtec TSW](https://www.samtec.com/products/tsw-107-07-g-d).

## Ratings and procurement

The BOM specifies resistor values/tolerances and capacitor voltage/dielectric families instead of generic parts. The 100 nF decouplers are 16 V X7R; 22 µF and 10 µF capacitors are 10 V X5R; 4.7 µF capacitors are 16 V X5R; 1 µF capacitors are 16 V X7R; oscillator capacitors are 50 V C0G. C_SYS_LOCAL uses a 0603 4.7 µF / 16 V X5R part to fit between the inductors. Confirm effective capacitance under DC bias as part of the open power review.

The chosen 2.2 µH inductors specify 2.4 A saturation current at 30% inductance drop, 1.8 A temperature-rise current, and 0.116 Ω maximum DCR. Selecting these parts does not qualify the existing 0.1 mm power traces or converter current budget. Crystal parts have explicit load and ESR specifications; oscillator startup and board parasitics have not been measured.

The 2026-09-20 JLC search-index snapshot is saved in `../design/assembly-stock.json`. **C161692 (the two four-pin JST GH connectors) showed only two pieces in stock.** That is not sufficient assurance for an assembly run, especially with attrition. Replenish/pre-order or consign the exact connectors before ordering; otherwise populate them manually. No parts have been reserved or ordered. The remaining selected SMT codes returned stock, but this snapshot is not a live allocation.

## JLCPCB process settings

JLCPCB's [published capabilities](https://jlcpcb.com/capabilities/pcb-capabilities) support 0.15 mm through drills on multilayer boards, with a minimum 0.25 mm via pad. This board uses 0.30 mm pads, a 0.15 mm pad-minus-drill diameter difference. Choose the 0.15 mm via option; it attracts an additional charge. The 0.1 mm trace/space design requires the compatible 1 oz outer-copper process, not the 2 oz option. No filled/capped vias are needed for this no-via-in-pad layout.

## Regenerate

```sh
npm run build:site
npm run audit:copper
node scripts/export-assembly.mjs
python3 scripts/check-assembly.py
node scripts/render-assembly.mjs
```

The supplier-library rotation mapping has been checked in software. Confirm the exact BOM/CPL against the assembler's final placement preview before placing an order; that supplier-side job review has not been performed.