seveibar/am3352-dev-board-4layer-dogbone

STATUS.md

> **Version 0.1.5:** tscircuit 0.0.2615 builds with zero errors; the 34 missing-connection errors are resolved. See [UPGRADE.md](UPGRADE.md). Detailed geometry reports below retain their previous build hashes.

# Four-layer validation status

Circuit JSON SHA-256: `d75afa3436b49908533fa273a58e4d9a8bc65c04031373de97ce66584f0430b6`.

- Runtime: tscircuit `0.0.2594`, core `0.0.1944`, checks `0.0.203`.
- Native `tsci build --site`: passed, zero DRC errors.
- Board: 70 × 60 × 1.2 mm; four copper layers.
- Components: 185; through vias: 421.
- Independent geometry: all 138 nets connected; zero clearance violations at the audit's 3 µm comparison tolerance.
- DDR: all 19 checks pass; largest measured group skew 0.019585 mm. Graph contacts use 1 µm resolution, so sub-micrometre numeric differences are not physical accuracy claims.
- Each matched DDR net uses three vias and 2.4 mm of vertical barrel travel.
- No-via-in-pad audit: passed, zero pad overlaps and 0.1 mm annulus clearance on both faces.
- Filled/capped via sites: 0; see the generated manifest.
- TypeScript, routing consistency, layer checks and validator regression tests pass.

Reports are tied to the compiled circuit hash. Regenerate them after any edit. Native advisory warnings remain: `{"pcb_component_missing_courtyard_warning": 1, "schematic_component_styling_warning": 2, "source_component_pins_underspecified_warning": 2, "source_no_ground_pin_defined_warning": 2, "source_no_power_pin_defined_warning": 3, "source_refdes_convention_warning": 1, "supplier_footprint_mismatch_warning": 151}`. These are not counted as DRC errors.

See README.md for the scope of verification and the remaining fabrication/SI review.