seveibar/am3352-dev-board-4layer-dogbone

ROUTING.md

# Four-layer routing

The TSX custom router in `design/replay-router.ts` replays the saved, validated copper in `design/routed-copper.json`. It rejects changed endpoint placement and invalid layer names. tscircuit generates the ground pour and runs native DRC after replay.

The completed route uses top, inner2 and bottom for signals and power, with an explicit ground pour on inner1. The BGA pin mapping remains unchanged. DDR routes were generated with a negotiated-congestion maze router, then clearance-checked chamfered meanders were inserted to match their lengths. Three vias per matched net give equal used vertical travel. Native copper geometry, independent connectivity/clearance, planar lengths, and lengths including barrels are validated after the final build.

The existing USB pair skew constraint remains enforced. Local assembly-footprint clearance changes required a small USB route adjustment; the pair has not been rerouted together or qualified for impedance. The user deferred that review. DDR signal routes are unchanged by the assembly update.

L1–L3 and Y1/Y2 now use their manufacturer land patterns. The RTC crystal has an enforced top-copper body keepout; nearby capacitors and local copper were moved to provide assembly space. Supplier part numbers and placement rotations are recorded in the assembly directory.

The oscillator parts were placed closer to the CPU. Bottom capacitors C_U1_P14 and C_DDR7 moved 2.61 mm and 0.54 mm respectively; both rotated 90 degrees to free pad-safe escapes. C_U1_G5 moved 3.05 mm and rotated 90 degrees; its power pad remains 3.80 mm from its associated ball. R_VTP moved to the underside beside the processor dogbone. Both RTC oscillator nets stay on the top layer without vias. The reset pull resistor remains attached to its routed DDR reset net.

## Rebuild safeguards

- `verify.mjs` compares every saved route against the compiled route, rejects native errors, and requires a current passing independent physical audit.
- `audit-copper.py --strict` tests real pad, trace, via and rendered-pour geometry, including all layers of through vias.
- `check-four-layer-stack.py` rejects nonexistent layers.
- `check-ddr-skew.py --strict` measures all 47 DDR ball-to-ball paths and checks 19 length groups independently of native DRC.
- `test-ddr-validator.py` verifies rejection of skewed and uniformly overlong buses. `test-via-travel.py` covers barrel path accounting and unknown inner depths.
- Connectivity patches are installed reproducibly and tested against wrong-net, wrong-layer, via-isolation, pour-cutout and disconnected-pour cases.

Every SMT pad is included in the hard via exclusion mask, even when the pad and via share a net. `check-no-via-in-pad.py --strict` independently verifies annulus-to-pad clearance in the generated circuit, on both faces.

The chosen stack differs from TI's four-layer reference stack. Copper connectivity and length matching do not validate impedance, return-current paths, power integrity or DDR timing. See README.md.