seveibar/am3352-dev-board-4layer-dogbone

README.md

> **Version 0.1.5:** tscircuit 0.0.2615 builds with zero errors; the 34 missing-connection errors are resolved. See [UPGRADE.md](UPGRADE.md). Detailed geometry reports below retain their previous build hashes.

# AM3352 four-layer dogbone board

Completed routed four-layer variant with no via-in-pad of `seveibar/am3352-dev-board@1.0.2`: 70 × 60 mm, 1.2 mm thick, with the original electrical netlist and DDR pin assignment. The oscillator parts were moved closer to their processor pins. C_U1_P14 was moved 2.61 mm and C_DDR7 was moved 0.54 mm; both were rotated 90 degrees to free dogbone escapes. C_U1_G5 moved 3.05 mm and rotated 90 degrees so R_VTP could sit on the underside next to the processor escape.

The native build passes with zero DRC errors. All 138 nets pass an independent physical copper connectivity and clearance audit. All 19 independent DDR length checks pass, including skew measured with the used vertical via spans. See [STATUS.md](STATUS.md), [DDR-SKEW.md](DDR-SKEW.md), and [ROUTING.md](ROUTING.md).

Assembly parts, manufacturer land patterns, supplier rotation mappings, and a separate manual-header BOM are included in [assembly/README.md](assembly/README.md). See [FABRICATION-REVIEW.md](FABRICATION-REVIEW.md) for the remaining electrical review.

The stack is top signals/components, inner1 ground, inner2 signals, bottom signals/components. Power rails are routed explicitly. The original eight-layer design is retained separately.

## Build and inspect

```sh
npm ci
python3 -m venv .venv
. .venv/bin/activate
pip install -r requirements.txt
npm run build:site
npm run audit:copper
npm run verify
npm run verify:layers
npm run verify:no-via-in-pad
npm run test:no-via-in-pad
npm run verify:ddr
npm run verify:ddr-topology
npm run test:ddr
npm run test:tooling
node scripts/export-assembly.mjs
python3 scripts/check-assembly.py
```

Serve `dist` with `python3 -m http.server 8000 --directory dist`, then open `http://localhost:8000/#file=index.circuit.tsx`. The generated site includes the TSX file, PCB views, schematic and 3D view.

## Scope of verification

This is a completed routed design, not fabrication or signal-integrity signoff. Its three signal layers plus one ground plane differ from TI's signal/ground/power/signal reference stack. Dielectrics, impedance, layer-dependent delay and package delay still require an engineering review. No via annulus overlaps an SMT pad on either face; all have at least 0.1 mm clearance in the independent audit. The generated filled/capped-via manifest is empty.

The pinned dependencies receive three reproducible connectivity fixes during `npm ci`: layer/net-aware endpoint inference, physical via contacts, and contacts through actual rendered pour polygons. Each has regression checks. No timing constraints or DRC errors are suppressed. Historical routing experiments under `routing-work` are excluded from the downloadable package.