seveibar/am3352-dev-board-4layer-dogbone

Defines PCB footprints and pin mappings for a TI AM3352ZCZ100 processor, JST GH connectors, and assembly-part lookup helpers for capacitors, resistors, and headers.

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DDR-SKEW.md

# Independent DDR length verification

Measured directly from the final circuit JSON, without using the built-in DRC. Trace edges use unrounded centerline geometry and graph junctions use 1 µm resolution.

All matched nets follow top → inner2 → bottom → top, or the reverse intermediate-layer order. Both paths traverse exactly twice the 1.2 mm board thickness. The resulting 2.4 mm vertical travel does not require an assumed inner-layer depth. The checker collapses graph-only intermediate nodes at each via before measuring used barrel travel.

Planar targets are 18.18 mm for byte 0, 12.195 mm for byte 1, and 35.02 mm for address/control/clock. Including barrels, these are 20.58, 14.595 and 37.42 mm. The placement-derived maximum checks below are explicitly planar; delay and impedance are not simulated.

| Check | Result | Skew / maximum (mm) | Limit (mm) |
|---|---|---:|---:|
| Byte 0: DQ + DM | PASS | 0.019584 | 0.635 |
| Byte 0: DQ + DM + DQS envelope | PASS | 0.019585 | 0.635 |
| DQS0 differential pair | PASS | 0.000002 | 0.127 |
| Byte 1: DQ + DM | PASS | 0.009887 | 0.635 |
| Byte 1: DQ + DM + DQS envelope | PASS | 0.009887 | 0.635 |
| DQS1 differential pair | PASS | 0.000001 | 0.127 |
| CK differential pair | PASS | 0.000001 | 0.127 |
| Address/control + CK envelope | PASS | 0.000010 | 0.635 |
| Byte 0: placement-derived maximum length | PASS | 18.180001 | 18.600 |
| Byte 1: placement-derived maximum length | PASS | 12.195001 | 12.200 |
| Address/control + CK nominal length | PASS | 35.020004 | 36.290 |
| Byte 0: DQ + DM including vias | PASS | 0.019584 | 0.635 |
| Byte 0: DQ + DM + DQS envelope including vias | PASS | 0.019585 | 0.635 |
| DQS0 differential pair including vias | PASS | 0.000002 | 0.127 |
| Byte 1: DQ + DM including vias | PASS | 0.009887 | 0.635 |
| Byte 1: DQ + DM + DQS envelope including vias | PASS | 0.009887 | 0.635 |
| DQS1 differential pair including vias | PASS | 0.000001 | 0.127 |
| CK differential pair including vias | PASS | 0.000001 | 0.127 |
| Address/control + CK envelope including vias | PASS | 0.000010 | 0.635 |

The address/control nominal planar interval is 33.75–36.29 mm. Source: [TI AM335x datasheet, Tables 7-68 and 7-69](https://www.ti.com/lit/ds/symlink/am3352.pdf).

The pinned native checker uses 1.6 mm per via. Equal three-via counts mean this constant offset cancels in its skew checks; the independent barrel calculation above uses the actual 1.2 mm board thickness.

| Net | Planar length (mm) | Including used barrels (mm) | Vias on path |
|---|---:|---:|---:|
| DDR_A0 | 35.019999 | 37.419999 | 3 |
| DDR_A1 | 35.020000 | 37.420000 | 3 |
| DDR_A10 | 35.019998 | 37.419998 | 3 |
| DDR_A11 | 35.019998 | 37.419998 | 3 |
| DDR_A12 | 35.020001 | 37.420001 | 3 |
| DDR_A2 | 35.020001 | 37.420001 | 3 |
| DDR_A3 | 35.020000 | 37.420000 | 3 |
| DDR_A4 | 35.020004 | 37.420004 | 3 |
| DDR_A5 | 35.019995 | 37.419995 | 3 |
| DDR_A6 | 35.019999 | 37.419999 | 3 |
| DDR_A7 | 35.019997 | 37.419997 | 3 |
| DDR_A8 | 35.019999 | 37.419999 | 3 |
| DDR_A9 | 35.020000 | 37.420000 | 3 |
| DDR_BA0 | 35.020001 | 37.420001 | 3 |
| DDR_BA1 | 35.019999 | 37.419999 | 3 |
| DDR_BA2 | 35.020000 | 37.420000 | 3 |
| DDR_CASn | 35.020000 | 37.420000 | 3 |
| DDR_CK | 35.020001 | 37.420001 | 3 |
| DDR_CKE | 35.020000 | 37.420000 | 3 |
| DDR_CKn | 35.020000 | 37.420000 | 3 |
| DDR_CSn0 | 35.019995 | 37.419995 | 3 |
| DDR_D0 | 18.160416 | 20.560416 | 3 |
| DDR_D1 | 18.179998 | 20.579998 | 3 |
| DDR_D10 | 12.194999 | 14.594999 | 3 |
| DDR_D11 | 12.185114 | 14.585114 | 3 |
| DDR_D12 | 12.194998 | 14.594998 | 3 |
| DDR_D13 | 12.194999 | 14.594999 | 3 |
| DDR_D14 | 12.195001 | 14.595001 | 3 |
| DDR_D15 | 12.194999 | 14.594999 | 3 |
| DDR_D2 | 18.179998 | 20.579998 | 3 |
| DDR_D3 | 18.179998 | 20.579998 | 3 |
| DDR_D4 | 18.180000 | 20.580000 | 3 |
| DDR_D5 | 18.179998 | 20.579998 | 3 |
| DDR_D6 | 18.180000 | 20.580000 | 3 |
| DDR_D7 | 18.179998 | 20.579998 | 3 |
| DDR_D8 | 12.195000 | 14.595000 | 3 |
| DDR_D9 | 12.195000 | 14.595000 | 3 |
| DDR_DQM0 | 18.179996 | 20.579996 | 3 |
| DDR_DQM1 | 12.195000 | 14.595000 | 3 |
| DDR_DQS0 | 18.180001 | 20.580001 | 3 |
| DDR_DQS1 | 12.194999 | 14.594999 | 3 |
| DDR_DQSn0 | 18.179999 | 20.579999 | 3 |
| DDR_DQSn1 | 12.194998 | 14.594998 | 3 |
| DDR_ODT | 35.020000 | 37.420000 | 3 |
| DDR_RASn | 35.019994 | 37.419994 | 3 |
| DDR_RESETn | 28.595417 | 30.995417 | 3 |
| DDR_WEn | 35.020000 | 37.420000 | 3 |

Circuit JSON SHA-256: `d75afa3436b49908533fa273a58e4d9a8bc65c04031373de97ce66584f0430b6`.