sangit/dataset-srj11-45-degree

This code defines a PCB layout with test points, obstacles, and routed traces, including components like rotated and twin pads for physical hardware design.

Version
0.1.0
License
unset
Stars
0

circuits/sample007.circuit.simple-route.json

{
  "simpleRouteJson": {
    "bounds": {
      "minX": -9.5,
      "maxX": 9.5,
      "minY": -4.05,
      "maxY": 4.05
    },
    "obstacles": [
      {
        "type": "oval",
        "layers": [
          "top"
        ],
        "center": {
          "x": -7.4,
          "y": -1.3
        },
        "width": 1.1,
        "height": 1.1,
        "connectedTo": [
          "pcb_smtpad_0",
          "connectivity_net0",
          "source_trace_0",
          "source_port_0",
          "source_port_1",
          "pcb_smtpad_0",
          "pcb_port_0",
          "pcb_smtpad_1",
          "pcb_port_1"
        ]
      },
      {
        "type": "oval",
        "layers": [
          "top"
        ],
        "center": {
          "x": 7.4,
          "y": 1.3
        },
        "width": 1.1,
        "height": 1.1,
        "connectedTo": [
          "pcb_smtpad_1",
          "connectivity_net0",
          "source_trace_0",
          "source_port_0",
          "source_port_1",
          "pcb_smtpad_0",
          "pcb_port_0",
          "pcb_smtpad_1",
          "pcb_port_1"
        ]
      },
      {
        "type": "rect",
        "layers": [
          "top"
        ],
        "center": {
          "x": -1.1752155492837888,
          "y": 2.674784450716211
        },
        "width": 2.255,
        "height": 2.1566756826189697,
        "connectedTo": [
          "pcb_smtpad_2",
          "connectivity_net11",
          "source_port_2",
          "pcb_smtpad_2",
          "pcb_port_2"
        ]
      },
      {
        "type": "rect",
        "layers": [
          "top"
        ],
        "center": {
          "x": -2.624784450716211,
          "y": 1.2252155492837888
        },
        "width": 2.255,
        "height": 2.1566756826189697,
        "connectedTo": [
          "pcb_smtpad_2",
          "connectivity_net11",
          "source_port_2",
          "pcb_smtpad_2",
          "pcb_port_2"
        ]
      },
      {
        "type": "rect",
        "layers": [
          "top"
        ],
        "center": {
          "x": 2.624784450716211,
          "y": -1.2252155492837888
        },
        "width": 2.255,
        "height": 2.1566756826189697,
        "connectedTo": [
          "pcb_smtpad_3",
          "connectivity_net12",
          "source_port_3",
          "pcb_smtpad_3",
          "pcb_port_3"
        ]
      },
      {
        "type": "rect",
        "layers": [
          "top"
        ],
        "center": {
          "x": 1.1752155492837888,
          "y": -2.674784450716211
        },
        "width": 2.255,
        "height": 2.1566756826189697,
        "connectedTo": [
          "pcb_smtpad_3",
          "connectivity_net12",
          "source_port_3",
          "pcb_smtpad_3",
          "pcb_port_3"
        ]
      }
    ],
    "connections": [
      {
        "name": "source_trace_0",
        "source_trace_id": "source_trace_0",
        "pointsToConnect": [
          {
            "x": -7.4,
            "y": -1.3,
            "layer": "top",
            "pointId": "pcb_port_0",
            "pcb_port_id": "pcb_port_0"
          },
          {
            "x": 7.4,
            "y": 1.3,
            "layer": "top",
            "pointId": "pcb_port_1",
            "pcb_port_id": "pcb_port_1"
          }
        ]
      }
    ],
    "layerCount": 2,
    "minTraceWidth": 0.1
  },
  "connMap": {
    "netMap": {
      "connectivity_net0": [
        "source_trace_0",
        "source_port_0",
        "source_port_1",
        "pcb_smtpad_0",
        "pcb_port_0",
        "pcb_smtpad_1",
        "pcb_port_1"
      ],
      "connectivity_net11": [
        "source_port_2",
        "pcb_smtpad_2",
        "pcb_port_2"
      ],
      "connectivity_net12": [
        "source_port_3",
        "pcb_smtpad_3",
        "pcb_port_3"
      ]
    },
    "idToNetMap": {
      "source_trace_0": "connectivity_net0",
      "source_port_0": "connectivity_net0",
      "source_port_1": "connectivity_net0",
      "pcb_smtpad_0": "connectivity_net0",
      "pcb_port_0": "connectivity_net0",
      "pcb_smtpad_1": "connectivity_net0",
      "pcb_port_1": "connectivity_net0",
      "source_port_2": "connectivity_net11",
      "pcb_smtpad_2": "connectivity_net11",
      "pcb_port_2": "connectivity_net11",
      "source_port_3": "connectivity_net12",
      "pcb_smtpad_3": "connectivity_net12",
      "pcb_port_3": "connectivity_net12"
    }
  }
}