rushabhcodes/desk-fidget-counter

validation/logs/native-fresh.txt

Building 1 file(s)...
Building index.circuit.tsx...
Generating circuit JSON...
Wrote debug artifact: dist/autorouter-debug/reve3-via-margin/placement-unrouted.png
Autorouting <board#799 name=".DESK_KNOB_REVE3" /> phase 1/1 "Whole two-layer board" start: connections=45, obstacles=250, previous_traces=0, router=tscircuit, version=beta_pipeline9, solver=AutoroutingPipelineSolver9_PreloadedTraceGraph, effort=2x, cache=miss, cache_id=8efffac3/579a5e70
  connections: USB_CC1_RD, USB_CC2_RD, MCU_VBAT_DECAP, MCU_VBAT_GROUND, MCU_VDDA_DECAP, MCU_VSSA_DECAP, MCU_VDD1_DECAP, MCU_VSS1_DECAP, MCU_VDDIO_DECAP, MCU_VSS2_DECAP, MCU_VDD2_DECAP, MCU_VSS3_DECAP, MCU_VDDA_LOCAL_BULK, MCU_VDDA_LOCAL_RETURN, MCU_VDDIO_LOCAL_BULK, MCU_VDDIO_LOCAL_RETURN, net.GND, net.V3V3, net.VBUS, net.PERIPH_3V3, net.PERIPH_EN, net.NRST, net.BOOT0, net.MODE_BTN, net.USB_DM, net.USB_DP, net.SWDIO, net.SWCLK, net.SCL, net.SDA, net.CC1, net.CC2, net.IR_A, net.OPT_A, net.OPT_B, net.ENC_A, net.ENC_B, net.LCD_RST, net.LCD_BL, net.LCD_CS, net.SPI_SCK, net.LCD_DC, net.SPI_MOSI, net.LCD_SCK, net.LCD_MOSI
  phase 1/1 "Whole two-layer board" progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=topologyPlanningSolver steps=1 progress=16% iterations_per_second=63 elapsed=1.5s
  phase 1/1 "Whole two-layer board" progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=highDensityForceImproveSolver steps=29 progress=56% iterations_per_second=430 elapsed=11.7s
  phase 1/1 "Whole two-layer board" progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=globalDrcForceImproveSolver steps=47 progress=80% iterations_per_second=2 elapsed=22.4s
  phase 1/1 "Whole two-layer board" progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=pipeline9JointDrcRepairSolver steps=73 progress=85% iterations_per_second=1500 elapsed=32.5s
  phase 1/1 "Whole two-layer board" progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=pipeline9JointDrcRepairSolver steps=98 progress=87% iterations_per_second=3087 elapsed=42.8s
  phase 1/1 "Whole two-layer board" progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=effortCleanupSolver steps=127 progress=88% iterations_per_second=2092 elapsed=53.0s
  phase 1/1 "Whole two-layer board" done: routed_traces=118, jumpers=0, errors=0, elapsed=56.2s
Wrote debug artifact: dist/autorouter-debug/reve3-via-margin/phase-0-routed.png
Could not save autorouting paths for subcircuit_source_group_0: Routes contain a junction or endpoint that cannot select a unique PCB port
Wrote debug artifact: dist/autorouter-debug/reve3-via-margin/board.meta.json
Circuit JSON written to dist/index/circuit.json
Trace [.U1 > .VSSA to .C8 > .pin2] is routed thinner than requested (requested: 0.15mm, actual: 0.1mm).
Trace [.U1 > .VSS1 to .C9 > .pin2] is routed thinner than requested (requested: 0.15mm, actual: 0.1mm).
Trace [.U1 > .VSS2 to .C10 > .pin2] is routed thinner than requested (requested: 0.15mm, actual: 0.1mm).
Trace [.U1 > .VDD2 to .C11 > .pin1] is routed thinner than requested (requested: 0.15mm, actual: 0.1mm).

Build complete
  Circuits  1 passed
  Options   autorouter-debug
  Output    dist

✓ Done
Build exiting with code 0: build finished successfully