rushabhcodes/desk-fidget-counter

routing/README.md

# Native two-layer autorouting

`index.circuit.tsx` uses tscircuit's built-in `auto_local`, `beta_pipeline7`, effort `2x`. All connections, including USB, power, ground and local decoupling, are generated by that autorouter. There is no custom routing function, coordinate repair, manual PCB copper/via, external routing engine or stored-path import.

The first native phase routes 14 named MCU bypass/bulk branches; the unindexed second phase routes the remaining board around that copper. Both request 0.15 mm tracks, 0.20 mm track/pad clearance and larger via margins. Board acceptance follows [the documented JLCPCB two-layer/1 oz rules](../reference/fabrication-rules.json): ordinary tracks and track/via gaps ≥0.10 mm, component pad-to-pad ≥0.15 mm and copper-to-edge ≥0.30 mm. The native solver retains some legal neck-downs; the narrowest is **0.115710653 mm**. Four explicitly requested MCU bypass/return branches remain ≥0.15 mm, including VSSA→C8. The local decoupling length limit remains 4 mm.

The validated result contains **118 routed traces and 136 vias**. Vias use Ø0.30 mm drills and Ø0.60 mm pads. The phase's 1.0 mm via-hole spacing is a routing request; final via drill-edge acceptance is 0.20 mm, with component PTH spacing checked separately at 0.45 mm. No copper errors or shorts are waived.

A 0.4 mm copper guard surrounds the original 34.6×40.6 mm display window. USB locating holes have circular copper guards. `allowPlacements` permits connector bodies above these spaces, while copper stays blocked. Component placements and the original large window are retained. The logical CC1 resistor trace is declared resistor→connector; reversing that electrically symmetric declaration changes the native solver's route selection and avoids the previous SBU2 collision.

The final build has **zero error records** and one cosmetic style warning: an ENC_B bottom segment is 6.10° away from a preferred 45° direction. It passes electrical and manufacturing rules; it has not been manually straightened. See [the validation record](../validation/REPORT.md).

Pinned toolchain: tscircuit 0.0.3077, core 0.0.2267, capacity-autorouter 0.0.1038, Bun 1.3.3. The project allows 20 minutes per build worker. CLI routing caches and debug output are ignored by Git and never imported into source.

```sh
bunx tsci build index.circuit.tsx --autorouter-debug --autorouter-dump-srj all
bun validation/check-design.mjs
bun run check:shorts
```

Before accepting a changed layout, repeat connectivity, schematic/PCB placement, exact-footprint, full native build and Gerber-derived shorts checks. The independent KiCad check in [manufacturing guidance](../manufacturing/README.md) verifies the exported geometry and requires all native trace/via coordinates and widths to remain unchanged.