runpatrick/sa-sim-pcb

sim/trace-width-audit.md

# SA-SIM v1 — Trace Width Audit

**Standard:** IPC-2221 Class 2 (commercial electronics, 10°C temperature rise, internal 1oz copper layer)
**Board:** SA-SIM v1, 40 mm × 40 mm, 4-layer (1oz outer / 0.5oz inner), FR-4 1.6 mm

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## Minimum Trace Widths by Net

| Net | Min Width | Reason | Status |
|---|---|---|---|
| VBAT, BAT_P | 0.50 mm | 1.6 A BG95 TX peak (DC ≈ 1.5 A → 0.5 mm internal 1oz), with 30% margin | TARGET |
| VSYS | 0.50 mm | Battery rail to all converters, ≤ 2 A | TARGET |
| _3V3 | 0.30 mm | ≤ 500 mA (sum of all 3V3 loads) | TARGET |
| _1V8 | 0.15 mm | ≤ 200 mA analog rail | TARGET |
| GND | (pour, n/a) | Full copper pour both layers | MET |
| I2C_SDA, I2C_SCL | 0.15 mm | < 10 mA, signal | TARGET |
| MODEM_TX/RX | 0.15 mm | 115200 baud, 1.8 V level via shifter | TARGET |
| SWDIO/SWDCLK | 0.15 mm | Debug | TARGET |
| USB_DM/DP | 0.18 mm w / 0.10 mm gap (90 Ω diff pair, 0.2 mm dielectric) | USB 2.0 spec | TARGET |
| ANT feed (BG95 → ant) | 0.38 mm | 50 Ω microstrip, 0.2 mm dielectric, εr = 4.4 | TARGET |

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## IPC-2221 Basis (Class 2, Internal Layer, 1oz Cu, 10°C Rise)

IPC-2221 Table 6-1, external conductors (10°C rise, 1oz Cu):

| Current (A) | Min Width (mm) |
|---|---|
| 0.5 | 0.15 |
| 1.0 | 0.30 |
| 1.5 | 0.45 |
| 2.0 | 0.58 |

The VBAT / VSYS targets of 0.50 mm cover the worst-case BG95 TX burst current (1.6 A peak per Quectel BG95 HW Design Guide §3.3) with 30% design margin added. The 0.30 mm width for _3V3 covers the expected ≤ 500 mA aggregate load across MCU, IMU, fuel gauge, and charger control logic.

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## Differential Pair — USB_DM / USB_DP

USB 2.0 Full Speed requires a 90 Ω ±10% characteristic differential impedance. Using the JLCPCB 4-layer stack (top copper 0.035 mm, top-to-L2 dielectric 0.20 mm FR-4, εr = 4.4):

- Trace width: **0.18 mm**
- Gap (edge-to-edge): **0.10 mm**
- Calculated Zdiff ≈ 90 Ω (via IPC-2141 coplanar waveguide approximation)

Route D+ and D− as a tightly coupled differential pair from J1 USB-C connector through D1 ESD array to IC1 USBD_DP/USBD_DM pins. Keep equal trace lengths (skew < 100 ps = < 15 mm at FR-4 Vp ≈ 0.6c). Minimize vias on this path.

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## Antenna Feed — BG95.RF_OUT → ANT1

A dedicated 50 Ω microstrip on top layer with L2 ground reference directly below. Trace width 0.38 mm yields Z₀ ≈ 46–50 Ω on the JLCPCB 4-layer stackup (see FAB_REPORT.md §10 for full derivation). Total feed length < 15 mm. π-match network (L_ANT_S1 / C_ANT_SH / L_ANT_S2) must be on the same top-layer segment with no layer transitions.

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> **Note:** Status TARGET = autorouter must be configured to enforce this min trace width per net. Add `<tracewidth>` overrides on these nets before fab export.