runpatrick/sa-sim-pcb

sim/power-on.spice

* SA-SIM v1 — Power-On SPICE simulation
* ======================================
* Models the power tree only. Behavioural models for the regulators
* (TPS62840, TPS7A02) and charger (BQ25180) — not pin-accurate, but
* captures rise time, current draw, and inrush envelope.
*
*   V_VBUS (5V from USB-C)
*       │
*       ▼
*    BQ25180 (linear charger, ~1A max)
*       │
*       ▼
*   V_SYS  (battery rail, ~3.7-4.2V depending on charge state)
*       │
*       ▼
*    TPS62840 (buck, 3.3V out, 750mA max, FB div 390k/100k)
*       │
*       ▼
*   V_3V3
*       │
*       ▼
*    TPS7A02 (LDO, 1.8V out, 200mA max, internal FB)
*       │
*       ▼
*   V_1V8
*
* Run:  ngspice -b sim/power-on.spice -o sim/power-on.results.txt

.title SA-SIM v1 power-on

* ─────────── INPUT: USB-C VBUS, ramps 0→5V over 1ms (typical USB plug-in) ───
V_VBUS  vbus_load 0 PULSE(0 5 0 1m 1n 999m 1)

* ─────────── BATTERY: 1S Li-Po @ 3.85V, 1Ω ESR, 700mAh nominal ──────────────
V_BAT  bat_raw 0 DC 3.85
R_BAT_ESR  bat_raw bat 1

* ─────────── BQ25180 (linear charger model) ─────────────────────────────────
* Behavioural: VBUS → VSYS via diode-OR; charges battery via current source.
* Use ngspice u() step function (u(x)=1 if x>0, else 0) instead of if().
*
* When VBUS>3.5V: vsys_from_vbus = vbus - 0.3, else = 0
B_VSYS_FROM_VBUS  vsys_from_vbus 0 V = (V(vbus_load) - 0.3) * u(V(vbus_load) - 3.5)
B_VSYS_FROM_BAT   vsys_from_bat  0 V = V(bat)
* Diode-OR (both candidate rails feed VSYS via Schottky-like model)
D_OR_VBUS  vsys_from_vbus vsys DSCHOTTKY
D_OR_BAT   vsys_from_bat  vsys DSCHOTTKY
.model DSCHOTTKY D(IS=1u N=1.05 RS=0.05)

* Bulk caps on VSYS (charger output 4.7uF + tantalum 10uF + bg95 4.7uF)
C_VSYS_BULK  vsys 0 19.4u IC=0
R_VSYS_LK    vsys 0 1Meg

* ─────────── TPS62840 buck (behavioural, 3.3V out @ 750mA) ──────────────────
* Modelled as voltage-controlled source: enables when VSYS > 2.0V.
* Soft-start: tSS ~ 2ms (datasheet 0.6-1ms typ, conservative).
* Output proportional to VSYS up to 3.3V regulated.
* u(V(vsys)-2.0) gates the regulator on.
B_3V3  v3v3_internal 0 V = 3.3 * u(V(vsys)-2.0) * (1 - exp(-(time)/2m))
R_3V3_OUT  v3v3_internal v3v3 0.1
C_3V3      v3v3 0 1u IC=0

* Load on _3V3: nRF52840 idle ~50µA, peak BLE TX ~16mA — model 5mA average
R_3V3_LOAD v3v3 0 660

* ─────────── TPS7A02 LDO (behavioural, 1.8V out @ 200mA) ─────────────────────
* tSS ~ 5ms. Dropout 100mV @ 100mA. Gates on when V_3V3 > 1.95V.
B_1V8  v1v8_internal 0 V = 1.8 * u(V(v3v3)-1.95) * (1 - exp(-(time)/5m))
R_1V8_OUT  v1v8_internal v1v8 0.5
C_1V8      v1v8 0 1u IC=0

* Load on _1V8: BNO086 + analog ~10mA
R_1V8_LOAD v1v8 0 180

* ─────────── INRUSH MEASUREMENT ──────────────────────────────────────────────
* Sense resistor on VBUS to capture inrush current
V_SENSE  vbus_sense vbus_load DC 0
R_VBUS_SENSE  vbus_sense vbus 0.01
* Bulk cap representing all VBUS-side decoupling (USB ESD + charger input)
C_VBUS  vbus 0 4.7u IC=0
R_VBUS_LK vbus 0 1Meg

* ─────────── CONTROL: transient analysis 100ms ──────────────────────────────
.tran 100u 100m UIC

* ─────────── MEASUREMENTS ────────────────────────────────────────────────────
* Rise time: 10% → 90% of final value
.meas tran t_3v3_10pct WHEN V(v3v3)=0.33 RISE=1
.meas tran t_3v3_90pct WHEN V(v3v3)=2.97 RISE=1
.meas tran t_3v3_rise PARAM='t_3v3_90pct - t_3v3_10pct'
.meas tran v_3v3_final FIND V(v3v3) AT=99m

.meas tran t_1v8_10pct WHEN V(v1v8)=0.18 RISE=1
.meas tran t_1v8_90pct WHEN V(v1v8)=1.62 RISE=1
.meas tran t_1v8_rise PARAM='t_1v8_90pct - t_1v8_10pct'
.meas tran v_1v8_final FIND V(v1v8) AT=99m

* Inrush peak (current through VBUS sense)
.meas tran i_vbus_peak MAX I(V_SENSE) FROM=0 TO=10m
.meas tran i_vbus_avg AVG I(V_SENSE) FROM=10m TO=99m

* VSYS final value (charger output)
.meas tran v_vsys_final FIND V(vsys) AT=99m

.print tran V(vbus_load) V(vsys) V(v3v3) V(v1v8) I(V_SENSE)

.end