runpatrick/sa-sim-pcb

sim/decoupling-audit.md

# SA-SIM v1 — Per-IC Decoupling Audit

**Date:** 2026-04-30  
**Source:** `index.circuit.tsx` (1136 lines), cross-referenced against IC datasheets  
**Auditor:** Claude Code autonomous harness

---

## Summary

| Status | Count | ICs |
|--------|-------|-----|
| PASS | 2 | USB-C protection (D1, U6); Crystals (X1, Y1) |
| CONCERN | 6 | nRF52840, BNO086, BQ25180, BQ51013, TPS62840 (decoupling), TPS7A02 |
| FAIL | 3 | **TPS62840 FB divider (CRITICAL)**, BG95-M3, BQ27220 |

**CRITICAL (fab-blocking):** 1 — TPS62840 feedback divider sets VOUT ≈ 2.94 V, not 3.3 V  
**Total CONCERN/FAIL items:** 9

---

## IC Audit Sections

---

### nRF52840 (IC1)

**Datasheet reference:** Nordic nRF52840 PS v1.7 §4.3

| Pin/Rail | Datasheet Rec | Found in PCB | Status | Notes |
|----------|--------------|--------------|--------|-------|
| VDD (supply) | 100 nF per pin + 1× 4.7 µF bulk | `C_MCU_VDD` = 100 nF only; no 4.7 µF bulk | CONCERN | Missing 4.7 µF bulk cap. Only a single 100 nF on _3V3 near MCU; multiple VDD pins share it. Susceptible to supply droop during RF/flash ops. |
| AVDD | 100 nF + ferrite bead from VDD | `C_MCU_AVDD` = 100 nF on _3V3 directly; no ferrite | CONCERN | No ferrite isolating AVDD from digital VDD. Analog ADC performance may degrade. Low-risk if ADC is not used for precision measurement, but PS recommends ferrite. |
| DEC1 | 100 nF (internal LDO dec) | `C_MCU_DEC1` = 100 nF ✓ | PASS | |
| DEC2 | 100 nF (internal LDO dec) | `C_MCU_DEC2` = 100 nF ✓ | PASS | |
| DEC3 | 100 nF (internal LDO dec) | `C_MCU_DEC3` = 100 nF ✓ | PASS | |
| DEC4 | 100 nF (internal LDO dec) | `C_MCU_DEC4` = 100 nF ✓ | PASS | |
| DCCH/DCC (DC/DC mode) | 10 µH inductor + 4.7 µF if DC/DC enabled | `C_MCU_DCCH` = 100 nF; no DCC inductor | CONCERN | DC/DC mode not currently enabled (pin connected to `MCU_DCCH` net → 100 nF to GND). If DC/DC mode is enabled in firmware, a 10 µH DCC inductor and 4.7 µF cap are mandatory. Schematic should either add these or explicitly document DC/DC mode as disabled. |
| VDDH (high-voltage) | 1 µF if VDDH used | VDDHDMI tied to _3V3 (3.3 V domain) | PASS | VDDH not used in this design (no NFC). Tied to _3V3 per Nordic recommendation for 3.3 V-only systems. No separate cap needed. |
| VBUS (USB) | 4.7 µF + 100 nF | `C_VBUS` = 4.7 µF on VBUS rail; no dedicated 100 nF near MCU VBUS pin | CONCERN | The 4.7 µF VBUS cap exists (line 167) but is placed far from MCU (pcbX=8.1, Y=33.5). MCU VBUS detect pin (`VBUS_DETECT`) is a sense-only connection — USB D+/D- are not wired through the MCU, so this is lower risk. Nevertheless, a 100 nF close to the VBUS_DETECT pin is recommended for noise immunity. |

**Summary for IC1:** DEC1–DEC4 pass. Missing 4.7 µF bulk on VDD, ferrite on AVDD, and DC/DC mode components are unresolved. These are CONCERNs, not hard failures for initial bring-up, but should be addressed before production.

---

### BG95-M3 (U2)

**Datasheet reference:** Quectel BG95 Hardware Design Guide v1.4 §3.3

| Pin/Rail | Datasheet Rec | Found in PCB | Status | Notes |
|----------|--------------|--------------|--------|-------|
| VBAT bulk | 100 µF tantalum/polymer + 10 µF X7R + 100 nF, close to module | `C_BG95_BAT1`=4.7 µF, `C_BG95_BAT2`=4.7 µF, `C_BG95_BAT3`=10 µF → **total 19.4 µF** | FAIL | **5× underbulked.** Quectel requires ≥100 µF of bulk storage to ride through LTE-M TX bursts (up to 2 A peak at 3.8 V). With only 19.4 µF, VBAT can sag below the 3.4 V UVLO threshold during transmission, causing modem reset or failed registration. Previously logged as FAB_REPORT.md Open Risk #6. A 100 µF 1210 polymer cap (e.g., Murata GRM32ER60J107ME20) must be added adjacent to the module. |
| VBAT per-pin 100 nF | 100 nF on each VBAT pin | Two 4.7 µF caps cover multiple pads; no dedicated 100 nF HF bypass per pin | CONCERN | The 4.7 µF 0402 caps provide some HF bypass, but Quectel recommends a 100 nF per-pin immediately at each VBAT pad for high-frequency decoupling. Given LGA form factor, at minimum one 100 nF 0402 should be placed at each VBAT pin cluster. |
| VDD_EXT (1.8 V out) | 1× 1 µF | net.MODEM_VDD_EXT exists, no cap found | CONCERN | The 1.8 V aux output from BG95 is routed to `MODEM_VDD_EXT` but no decoupling cap is placed on this net. The Quectel guide requires 1 µF. While VDD_EXT is currently not wired to MCU (noted in code comment), it still needs local decoupling for stability. |
| USIM_VCC | 1× 1 µF + 33 pF on each USIM line | `C_ESIM_VCC` = 100 nF (line 1108) on ESIM_VCC; no 33 pF ESD caps on USIM_DATA/CLK/RST | CONCERN | C_ESIM_VCC exists (100 nF) but is undersized — datasheet calls for 1 µF on USIM_VCC. The 33 pF ESD/filter caps on each SIM signal line are completely absent. These suppress EMI from the SIM interface clock and prevent ESD damage to the eSIM contacts. |

**Summary for U2:** VBAT bulk is a hard FAIL. VDD_EXT decoupling and USIM signal filtering are CONCERNs.

---

### BNO086 (U1)

**Datasheet reference:** CEVA BNO08X DS

| Pin/Rail | Datasheet Rec | Found in PCB | Status | Notes |
|----------|--------------|--------------|--------|-------|
| VDD | 100 nF close to pin | `C_IMU_VDD` = 100 nF on _3V3 ✓ | PASS | |
| VDDIO | 100 nF + 4.7 µF | `C_IMU_VDDIO` = 100 nF on _1V8 only | CONCERN | Missing 4.7 µF bulk on VDDIO rail. IMU draws current spikes during QUAT output bursts. Without bulk storage, the 1.8 V LDO output can droop and cause VDDIO brown-out resets on the IMU. A 4.7 µF 0402 X5R should be added on _1V8 near the IMU. |
| BOOTN/RESET | 10 k pullup recommended | Not explicitly found in search results for BNO-specific pullup | CONCERN | Confirm that BOOTN/RESET pin is properly pulled up. The BNO086 requires BOOTN held high for normal operation (active-low bootloader entry). The nRF52840 GPIO driving this should have a 10 k pullup or the BNO internal pullup enabled via firmware at init. |

**Summary for U1:** VDD pass. VDDIO missing bulk cap. BOOTN pullup should be verified.

---

### BQ25180 (U3)

**Datasheet reference:** TI SLUSDP3

| Pin/Rail | Datasheet Rec | Found in PCB | Status | Notes |
|----------|--------------|--------------|--------|-------|
| IN (VBUS input) | 4.7 µF X5R/X7R close to pin | `C_CHG_VIN` = 100 nF on VBUS (line 300); `C_VBUS` = 4.7 µF but placed far (pcbX=8.1) | CONCERN | The 100 nF `C_CHG_VIN` is placed locally near U3 (pcbX=27.1, Y=15) but is undersized — datasheet wants 4.7 µF. The 4.7 µF `C_VBUS` is far away and serves USB ESD protection, not charger IN decoupling. A dedicated 4.7 µF X5R 0402 close to the IN pin of U3 is needed. |
| PMID | 1 µF (per SLUSDP3 §8.2) | `C_PMID` = 4.7 µF (line 290) | PASS | Oversized but acceptable — more bulk is better here. |
| BAT output | 4.7 µF X5R close to pin | `C_BAT` = 4.7 µF on BAT_P (line 245, pcbX=48, Y=34) | CONCERN | `C_BAT` is placed at pcbX=48, Y=34, which is on the far east side of the board — far from U3 at pcbX=24, Y=15. This cap is not electrically close to the BAT pin. A dedicated 4.7 µF on BAT_P within ~3 mm of U3 pin 3 (BAT) is needed. |
| SYS output | 4.7 µF X5R close to pin | No dedicated C_CHG_SYS found on VSYS near U3 | CONCERN | The SYS pin drives VSYS rail. The nearest cap on VSYS is `C_BUCK_IN` = 10 µF at pcbX=25.1, Y=6 — somewhat close but not immediately adjacent to SYS pin (U3 at Y=15). No dedicated 4.7 µF close to U3 SYS pin. SLVSEY1 requires this for output stability under load transients. |

**Summary for U3:** PMID passes. IN, BAT, and SYS are all CONCERN due to missing or remotely placed caps.

---

### BQ27220 (U5)

**Datasheet reference:** TI SLUSCY9

| Pin/Rail | Datasheet Rec | Found in PCB | Status | Notes |
|----------|--------------|--------------|--------|-------|
| VCC | 100 nF + 1 µF (note: 1 µF MAX, ESD damage risk above) | `C_FG_VCC` = 100 nF only (line 447) | CONCERN | Missing 1 µF on VCC. SLUSCY9 §7.3 calls for both 100 nF and 1 µF. Also note the 1 µF maximum: do not use 4.7 µF or larger. |
| BAT pin | Connect through 1 kΩ+ series resistor from actual battery | BAT pin wired directly to `net.BAT_P` (no series resistor, lines 434–435) | FAIL | **Missing mandatory isolation resistor.** SLUSCY9 §7.3.1 explicitly requires a 1 kΩ (or larger) resistor in series between the fuel gauge BAT pin and the battery rail. Without it, a large discharge pulse from the battery passes directly through the fuel gauge's internal ADC input — risk of permanent ESD damage. This must be fixed before fab. |
| TS divider | NTC thermistor divider | `R_NTC_PU` (10 k pullup) and `R8` (NTC 10 k) present | PASS | Thermistor divider correctly implemented. |

**Summary for U5:** VCC cap incomplete (CONCERN). BAT direct connection without series resistor is a FAIL — datasheet explicitly prohibits this and cites ESD damage risk.

---

### BQ51013 (IC2)

**Datasheet reference:** TI SLUSC11

| Pin/Rail | Datasheet Rec | Found in PCB | Status | Notes |
|----------|--------------|--------------|--------|-------|
| AC1 | 22 µF X5R 0805 (resonant filter) | `C_QI_AC1` = 22 µF 0805 ✓ | PASS | |
| AC2 | 22 µF X5R 0805 (resonant filter) | `C_QI_AC2` = 22 µF 0805 ✓ | PASS | |
| VOUT | 22 µF X5R 0805 + 100 nF | `C_QI_VOUT` = 22 µF 0805; no dedicated 100 nF on QI_VOUT | CONCERN | The 22 µF cap is present but the companion 100 nF HF bypass on VOUT is missing. At Qi 110–205 kHz switching frequencies, the 100 nF provides critical HF decoupling that the 22 µF X5R cannot cover at frequency. |
| BOOT1 | 10 nF (between BOOT and AC1) | `C_QI_BOOT1` = 100 nF (line 386) | CONCERN | **10× oversized.** SLUSC11 specifies 10 nF for the boot strap cap. Using 100 nF slows the bootstrap charge time and can affect soft-start behavior. Should be changed to 10 nF 0402 (e.g., CL05B103KB5NNNC). |
| BOOT2 | 10 nF (between BOOT and AC2) | `C_QI_BOOT2` = 100 nF (line 387) | CONCERN | Same as BOOT1 — 10× oversized. |
| CLAMP1/2 | 100 nF (per SLUSC11) | `C_QI_CLAMP1` = 100 nF; `C_QI_CLAMP2` = 100 nF ✓ | PASS | |

**Summary for IC2:** AC1/AC2/CLAMP pass. VOUT missing 100 nF HF bypass. BOOT caps are 10× oversized.

---

### TPS62840 (IC3) Buck Converter

**Datasheet reference:** TI SLVSEY1

#### CRITICAL: FB Divider Voltage Error

The TPS62840 internal reference voltage is **V_REF = 0.6 V**. Output voltage is set by:

```
Vout = V_REF × (1 + R_FB_TOP / R_FB_BOT)
     = 0.6 × (1 + 390k / 100k)
     = 0.6 × 4.9
     = 2.94 V
```

**The design intends 3.3 V. The actual resistor values produce 2.94 V.**

The comment in `index.circuit.tsx` (line 493) even states the correct target bottom resistor is **86.6 kΩ** (standard E96 value: 86.6 kΩ exists in E96 series), but the placed part is **100 kΩ**. Using 86.6 kΩ:

```
Vout = 0.6 × (1 + 390k / 86.6k) = 0.6 × 5.503 = 3.30 V  ✓
```

| Pin/Rail | Datasheet Rec | Found in PCB | Status | Notes |
|----------|--------------|--------------|--------|-------|
| FB divider | R_top = 390 kΩ, R_bot = 86.6 kΩ → 3.3 V | R_FB_TOP = 390 kΩ ✓; R_FB_BOT = 100 kΩ ✗ | **FAIL — CRITICAL** | **VOUT will be 2.94 V, not 3.3 V.** Every 3.3 V device (nRF52840 min VDD = 1.7 V, but I2C bus levels, logic thresholds, and peripheral minimum ratings will malfunction). nRF52840 3.3 V SPI/I2C drive levels become ~2.7 V — below the 3.0 V minimum for some peripherals. **Change R_FB_BOT from 100 kΩ to 86.6 kΩ (E96: SUSUMU RR0402P-8662-D or equivalent).** |
| VIN cap | 4.7 µF X5R + 100 nF | `C_BUCK_IN` = 10 µF 0603 on VSYS | PASS | 10 µF exceeds 4.7 µF minimum. No dedicated 100 nF, but 10 µF 0603 ceramic covers HF adequately. |
| VOUT cap | 10 µF X5R 0603 + 100 nF | `C_BUCK_OUT` = 10 µF 0603 on _3V3 | PASS | 10 µF meets requirement. Same HF note as VIN — acceptable without separate 100 nF given the 0603 ceramic's self-resonance. |
| Inductor | 2.2 µH NR3015 | `L1` = 2.2 µH NR3015T2R2M ✓ | PASS | |

**Summary for IC3:** The inductor and capacitors pass. The FB divider is a **CRITICAL fab-stopping bug**.

---

### TPS7A02 (U4) LDO

**Datasheet reference:** TI SLVSDQ9

| Pin/Rail | Datasheet Rec | Found in PCB | Status | Notes |
|----------|--------------|--------------|--------|-------|
| VIN | 1 µF X5R 0402 | `C_LDO_IN` = 100 nF 0402 (line 524) | CONCERN | 10× undersized. SLVSDQ9 §9.2 requires 1 µF minimum on VIN for stability. 100 nF may cause LDO instability (oscillation) at high output current. Change to 1 µF 0402 X5R (e.g., CL05A105KA5NQNC). |
| VOUT | 1 µF X5R 0402 | `C_LDO_OUT` = 100 nF 0402 (line 525) | CONCERN | 10× undersized. Same instability risk as VIN. Change to 1 µF 0402 X5R. |
| NR/SS | 10 nF (sets noise reduction/soft-start time) | `C_LDO_NR` = 10 nF 0402 ✓ (line 526, CL05B103KB5NNNC) | PASS | Value correct. Note: the supplierPartNumbers for this cap references `LCSC.CAP_100N_0402` — this is a **BOM mismatch**: a 10 nF cap is listed under the 100 nF LCSC part number. The placed part number (CL05B103KB5NNNC = 10 nF) is correct, but the LCSC lookup key is wrong. Fix the `supplierPartNumbers` to use a 10 nF LCSC entry (e.g., C57112 for 470 nF is also wrong — needs correct 10 nF LCSC C code). |

**Summary for U4:** NR/SS value correct. VIN and VOUT caps are 10× undersized — risk of LDO oscillation. BOM has a LCSC part number mismatch on `C_LDO_NR`.

---

### USB-C Protection (J1, D1, U6)

**Reference:** ESDA6V1-5SC6 datasheet; SMAJ5.0CA datasheet

| Component | Recommendation | Found in PCB | Status | Notes |
|-----------|---------------|--------------|--------|-------|
| D1 (ESDA6V1-5SC6) | SOT-23-6 ESD array, no decoupling caps needed | Present, SOT-23-6, D+/D- protected | PASS | |
| U6 (SMAJ5.0CA TVS) | Bidirectional TVS, no decoupling caps needed | Present, SMA footprint | PASS | |
| CC1/CC2 pulldowns | 5.1 kΩ each | R_CC1, R_CC2 = 5.1 kΩ 0402 ✓ | PASS | Both CC resistors present and correct value. |
| VBUS decoupling | 4.7 µF bulk | `C_VBUS` = 4.7 µF 0402 ✓ | PASS | |

**Summary:** USB-C protection chain passes all checks.

---

### Crystals (X1 HFXO, Y1 LFXO)

**Reference:** nRF52840 PS §4.4; crystal manufacturer spec

| Item | Recommendation | Found in PCB | Status | Notes |
|------|---------------|--------------|--------|-------|
| HFXO load caps | 12 pF 0402, <5 mm from X1 | `C_HFXO1`, `C_HFXO2` = 12 pF 0402 ✓ | PASS | |
| LFXO load caps | 12 pF 0402 | `C_LFXO1`, `C_LFXO2` = 12 pF 0402 ✓ | PASS | |

**Summary:** Crystal decoupling passes.

---

## Recommendations

### CRITICAL — Must fix before fab

1. **TPS62840 R_FB_BOT: Change 100 kΩ to 86.6 kΩ**
   - Current Vout = 2.94 V. Target = 3.3 V.
   - Replace `R_FB_BOT` (line 496) with 86.6 kΩ E96 resistor.
   - Suggested LCSC: search for RR0402P-8662-D or equivalent 86.6 kΩ 1% 0402.
   - **Every 3.3 V component on the board depends on this rail.**

### HIGH — Fix before production (risk of hardware damage or field failure)

2. **BQ27220 BAT pin: Add 1 kΩ series resistor between BAT_P and U5 BAT pin**
   - SLUSCY9 §7.3.1 explicitly prohibits direct battery connection.
   - Add `R_FG_BAT` = 1 kΩ 0402 in series on the BAT_P → U5 BAT net.

3. **BG95-M3 VBAT bulk: Add 100 µF polymer/tantalum cap**
   - Current total: 19.4 µF. Required: ≥100 µF.
   - Add one 100 µF 1210 low-ESR polymer cap (e.g., Murata GRM32ER60J107ME20, LCSC lookup needed) adjacent to BG95 module.
   - Without this, modem will likely reset during LTE-M TX bursts.

### MEDIUM — Fix before production (functional/performance risk)

4. **TPS7A02 VIN/VOUT caps: Change 100 nF → 1 µF X5R 0402**
   - `C_LDO_IN` and `C_LDO_OUT` both need to be 1 µF per SLVSDQ9.
   - LDO stability requirement, not just decoupling preference.

5. **nRF52840 VDD: Add 4.7 µF bulk cap on _3V3 near IC1**
   - Single 100 nF is insufficient for MCU draw transients.
   - Add one 4.7 µF 0402 X5R (C_MCU_VDD_BULK) on _3V3 within 2 mm of IC1.

6. **BNO086 VDDIO: Add 4.7 µF on _1V8 near U1**
   - `C_IMU_VDDIO` = 100 nF is present but insufficient without bulk.
   - Add 4.7 µF 0402 X5R on _1V8 rail adjacent to IMU.

7. **BQ25180 IN: Add dedicated 4.7 µF X5R near U3 IN pin**
   - `C_CHG_VIN` = 100 nF is insufficient. Add 4.7 µF 0402 X5R on VBUS at U3.

8. **BQ25180 BAT: Add 4.7 µF X5R within 3 mm of U3 BAT pin**
   - `C_BAT` exists (4.7 µF) but is at pcbX=48, Y=34 — far from U3 at pcbX=24, Y=15.
   - Add a second 4.7 µF close to U3 or relocate `C_BAT`.

9. **BQ27220 VCC: Add 1 µF cap alongside C_FG_VCC**
   - `C_FG_VCC` = 100 nF. Add 1 µF X5R 0402 in parallel. Do not exceed 1 µF per SLUSCY9.

10. **BG95 VDD_EXT: Add 1 µF cap on MODEM_VDD_EXT net**
    - 1.8 V aux output from BG95 is unfiltered. Add 1 µF 0402 on this net.

11. **BG95 USIM interface: Add 33 pF on USIM_DATA, USIM_CLK, USIM_RST; upgrade ESIM_VCC cap to 1 µF**
    - Three 33 pF 0402 caps needed for EMI/ESD on SIM signal lines.
    - `C_ESIM_VCC` (100 nF) should be increased to 1 µF per Quectel HW guide.

### LOW — Clean up before production

12. **BQ51013 BOOT caps: Change C_QI_BOOT1/2 from 100 nF → 10 nF**
    - SLUSC11 specifies 10 nF bootstrap cap. 100 nF is 10× oversized.
    - Replace with 10 nF 0402 (e.g., CL05B103KB5NNNC = C57112 or equivalent).

13. **BQ51013 VOUT: Add 100 nF HF bypass alongside C_QI_VOUT**
    - A 100 nF in parallel with the 22 µF covers HF decoupling above the large-cap self-resonance.

14. **TPS7A02 C_LDO_NR: Fix LCSC part number mismatch**
    - `C_LDO_NR` is a 10 nF cap (value and mfr PN correct) but `supplierPartNumbers` references `LCSC.CAP_100N_0402`.
    - Add a `CAP_10N_0402` entry to the LCSC constants and update the reference.

15. **nRF52840 AVDD: Add ferrite bead between VDD and AVDD**
    - `C_MCU_AVDD` exists but AVDD connects directly to _3V3 with no isolation.
    - If ADC precision matters: add ferrite (e.g., BLM15BB221SH1D) + route through separate net `MCU_AVDD`.

16. **nRF52840 DCC mode documentation: Explicitly document DC/DC mode OFF**
    - If DC/DC mode will ever be enabled, the 10 µH + 4.7 µF DCC components must be added to the schematic now, even if DNP (do-not-populate).

---

## Conclusion

**Overall: NOT READY FOR FAB**

One CRITICAL fab-stopping bug was found:

> **The TPS62840 feedback divider (R_FB_BOT = 100 kΩ) produces VOUT = 2.94 V instead of 3.3 V. This will cause brownout or malfunction in every 3.3 V device on the board including the nRF52840 MCU, BNO086 IMU, and I2C bus.**  
> Fix: change R_FB_BOT to 86.6 kΩ (E96 standard value).

Two additional HIGH-severity issues require schematic changes before the board is sent for assembly:

- BQ27220 BAT pin direct battery connection (no 1 kΩ isolation resistor) — risk of ESD damage to fuel gauge
- BG95-M3 VBAT severely underbulked (19.4 µF vs 100 µF required) — risk of modem TX failure in field

After the three HIGH+ items are resolved, the remaining 12 MEDIUM/LOW items should be addressed in a second-pass review or incorporated as errata for production rev 1.1.