runpatrick/sa-sim-pcb

This code defines PCB footprints for various electronic modules, including BG95 cellular modem, BNO086 sensor, BQ25180 battery charger, and BQ27220 power management IC, detailing their physical pad layouts and key external features.

Version
1.0.6
License
unset
Stars
0

overlap-pairs-iter1.json

[
  {
    "type": "footprint_overlap",
    "a": "J1",
    "b": "C_MCU_DEC3",
    "msg": "pcb_smtpad J1.pin7 overlaps with pcb_smtpad C_MCU_DEC3.pin1"
  },
  {
    "type": "footprint_overlap",
    "a": "U6",
    "b": "C_BG95_BAT3",
    "msg": "pcb_smtpad U6.VBUS overlaps with pcb_smtpad C_BG95_BAT3.pin1"
  },
  {
    "type": "footprint_overlap",
    "a": "IC3",
    "b": "R_FB_TOP",
    "msg": "pcb_smtpad IC3.EN overlaps with pcb_smtpad R_FB_TOP.pin2"
  },
  {
    "type": "footprint_overlap",
    "a": "IC3",
    "b": "R_FB_TOP",
    "msg": "pcb_smtpad IC3.MODE overlaps with pcb_smtpad R_FB_TOP.pin2"
  },
  {
    "type": "footprint_overlap",
    "a": "C21",
    "b": "C_MCU_AVDD",
    "msg": "pcb_smtpad C21.pin1 overlaps with pcb_smtpad C_MCU_AVDD.pin1"
  },
  {
    "type": "footprint_overlap",
    "a": "C21",
    "b": "C_MCU_AVDD",
    "msg": "pcb_smtpad C21.pin1 overlaps with pcb_smtpad C_MCU_AVDD.pin2"
  },
  {
    "type": "pad_pad_clearance",
    "a": "J1",
    "b": "C_MCU_DEC3",
    "msg": "Pads pcb_port[.J1 > .pin7] and pcb_port[.C_MCU_DEC3 > .pin1] are too close (clearance: 0mm, minimum: 0.1mm)"
  },
  {
    "type": "pad_pad_clearance",
    "a": "U6",
    "b": "C_BG95_BAT3",
    "msg": "Pads pcb_port[.U6 > .VBUS] and pcb_port[.C_BG95_BAT3 > .pin1] are too close (clearance: 0mm, minimum: 0.1mm)"
  },
  {
    "type": "pad_pad_clearance",
    "a": "IC3",
    "b": "R_FB_TOP",
    "msg": "Pads pcb_port[.IC3 > .EN] and pcb_port[.R_FB_TOP > .pin2] are too close (clearance: 0mm, minimum: 0.1mm)"
  },
  {
    "type": "pad_pad_clearance",
    "a": "IC3",
    "b": "R_FB_TOP",
    "msg": "Pads pcb_port[.IC3 > .MODE] and pcb_port[.R_FB_TOP > .pin2] are too close (clearance: 0mm, minimum: 0.1mm)"
  },
  {
    "type": "pad_pad_clearance",
    "a": "C21",
    "b": "C_MCU_AVDD",
    "msg": "Pads pcb_port[.C21 > .pin1] and pcb_port[.C_MCU_AVDD > .pin1] are too close (clearance: 0mm, minimum: 0.1mm)"
  },
  {
    "type": "pad_pad_clearance",
    "a": "C21",
    "b": "C_MCU_AVDD",
    "msg": "Pads pcb_port[.C21 > .pin1] and pcb_port[.C_MCU_AVDD > .pin2] are too close (clearance: 0mm, minimum: 0.1mm)"
  },
  {
    "type": "pad_pad_clearance",
    "a": "IC1",
    "b": "C_MCU_AVDD",
    "msg": "Pads pcb_port[.IC1 > .NC20] and pcb_port[.C_MCU_AVDD > .pin1] are too close (clearance: 0.085mm, minimum: 0.1m"
  },
  {
    "type": "pad_pad_clearance",
    "a": "IC1",
    "b": "IC1",
    "msg": "Pads pcb_port[.IC1 > .DCCH] and pcb_port[.IC1 > .MODEM_RX] are too close (clearance: 0mm, minimum: 0.1mm)"
  },
  {
    "type": "pad_pad_clearance",
    "a": "IC1",
    "b": "R_SCL",
    "msg": "Pads pcb_port[.IC1 > .SCL] and pcb_port[.R_SCL > .pin1] are too close (clearance: 0.085mm, minimum: 0.1mm)"
  },
  {
    "type": "courtyard_overlap",
    "a": "D1",
    "b": "C_VBUS",
    "msg": "Courtyard of D1 overlaps with courtyard of C_VBUS"
  },
  {
    "type": "courtyard_overlap",
    "a": "U6",
    "b": "C_BG95_BAT3",
    "msg": "Courtyard of U6 overlaps with courtyard of C_BG95_BAT3"
  },
  {
    "type": "courtyard_overlap",
    "a": "U7",
    "b": "C_QI_VOUT",
    "msg": "Courtyard of U7 overlaps with courtyard of C_QI_VOUT"
  },
  {
    "type": "courtyard_overlap",
    "a": "L1",
    "b": "R_FB_TOP",
    "msg": "Courtyard of L1 overlaps with courtyard of R_FB_TOP"
  },
  {
    "type": "courtyard_overlap",
    "a": "C21",
    "b": "C_MCU_AVDD",
    "msg": "Courtyard of C21 overlaps with courtyard of C_MCU_AVDD"
  },
  {
    "type": "courtyard_overlap",
    "a": "C21",
    "b": "C_BG95_UART",
    "msg": "Courtyard of C21 overlaps with courtyard of C_BG95_UART"
  }
]