runpatrick/sa-sim-pcb
This code defines PCB footprints for various electronic modules, including BG95 cellular modem, BNO086 sensor, BQ25180 battery charger, and BQ27220 power management IC, detailing their physical pad layouts and key external features.
- Version
- 1.0.6
- License
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index.circuit.tsx
PCB
Schematic
// SA-SIM v1 — 50mm IP68 cellular puck tracker (FAB-READY synthesis)
//
// Stack: nRF52840 + BG95-M3 + BNO086 + BQ25180 + BQ51013 + BQ27220
// + TPS62840 buck + TPS7A02 LDO + USB-C + JST + eSIM + 32MHz/32kHz
//
// Every component has manufacturerPartNumber + supplierPartNumbers (LCSC).
// Every required net from the W1 punch list is wired via `connections` props
// (which generate traces under the hood — see tscircuit netlabel.md docs).
//
// LCSC C-numbers verified against live LCSC catalog by W2 sourcing audit.
// Where the legacy CLAUDE.md C-numbers were dead/wrong, current substitutes
// are documented inline and listed in FAB_REPORT.md.
//
// Pin assignments per W5 (lowest free GPIO first, lowest collision risk).
// Footprints per W3 (inline definitions in ./footprints/*.tsx).
import { nrf52840Footprint } from "./footprints/nrf52840"
import { bg95Footprint } from "./footprints/bg95"
import { bno086Footprint } from "./footprints/bno086"
import { bq25180Footprint } from "./footprints/bq25180"
import { bq51013Footprint } from "./footprints/bq51013"
import { bq27220Footprint } from "./footprints/bq27220"
import { tps62840Footprint } from "./footprints/tps62840"
import { tps7a02Footprint } from "./footprints/tps7a02"
import { usbcFootprint } from "./footprints/usbc"
import { jstph2Footprint } from "./footprints/jstph2"
import { esimFootprint } from "./footprints/esim"
import { crystalHfxoFootprint, crystalLfxoFootprint } from "./footprints/crystal"
// LCSC part numbers (verified live by W2; substitutes documented in FAB_REPORT.md)
const LCSC = {
CAP_4U7_0402: "C52923", // Samsung CL05A475MQ5NRNC 4.7µF 10V X5R 0402
CAP_10U_0603: "C19702", // Samsung CL10A106KP8NNNC 10µF 10V X5R 0603
CAP_100N_0402: "C1525", // Samsung CL05B104KO5NNNC 100nF 16V X7R 0402
CAP_22U_0805: "C45783", // Samsung CL21A226MAQNNNE 22µF 25V X5R 0805
CAP_470N_0402: "C307331", // Samsung CL05A474KP5NNNC 470nF 10V X5R 0402
CAP_12P_0402: "C2622", // Samsung CL05C120JB5NNNC 12pF C0G 0402
CAP_10U_TANT: "C7171", // AVX TAJB106K016RNJ 10µF 16V tantalum (B case ~3.5×2.8mm)
RES_5K1_0402: "C23186", // UNI-ROYAL 0402WGF5101TCE 5.1kΩ ±1% 0402
RES_4K7_0402: "C23162", // UNI-ROYAL 0402WGF4701TCE 4.7kΩ ±1% 0402
RES_10K_0402: "C25879", // UNI-ROYAL 0402WGF1002TCE 10kΩ ±1% 0402
RES_100K_0402: "C25741", // UNI-ROYAL 0402WGF1003TCE 100kΩ ±1% 0402
RES_86K6_0402: "C115175", // UNI-ROYAL 0402WGF8662TCE 86.6kΩ ±1% 0402 (FB bottom — gives Vout=3.3V exact with 390k top)
RES_390K_0402: "C25749", // UNI-ROYAL 0402WGF3903TCE 390kΩ ±1% 0402 (FB top)
RES_1K_0402: "C25585", // UNI-ROYAL 0402WGF1001TCE 1kΩ ±1% 0402 (BQ27220 BAT pin ESD series, etc.)
IND_2U2: "C349717", // Taiyo Yuden NR3015T2R2M 2.2µH NR3015 case
NTC_10K: "C26429", // Murata NCP15WF104F03RC 10kΩ B=3380K 0402
D_USB_ESD: "C2827672", // TECH PUBLIC ESDA6V1-5SC6 (USBLC6-2SC6 equivalent)
TVS_5V: "C85402", // Littelfuse SMAJ5.0CA bidirectional TVS
PFET_REVPOL: "C146249", // DMP2305U P-MOSFET SOT-23 reverse polarity
// ICs — sourced via LCSC search (W2 confirmed availability via parametric search)
IC_NRF52840: "C2652054", // Nordic nRF52840-QIAA-R QFN73
IC_BG95: "C5253760", // Quectel BG95-M3 LGA96 (sometimes via Arrow)
IC_BNO086: "C5446352", // CEVA/Hillcrest BNO086 LGA28
IC_BQ25180: "C2916341", // TI BQ25180YBGR WCSP9
IC_BQ27220: "C2615436", // TI BQ27220YZFR DSBGA12
IC_BQ51013: "C100450", // TI BQ51013BRHLR QFN28
IC_TPS62840: "C2913012", // TI TPS62840DLCR X2SON8
IC_TPS7A02: "C2837085", // TI TPS7A0218PDQNR X2SON6
CONN_USBC: "C2682202", // GCT USB4085-GF-A USB-C 6-pin
CONN_JST: "C173754", // JST S2B-PH-K-S
XTAL_HFXO: "C383439", // Abracon ABM8-272-T3 32MHz
XTAL_LFXO: "C32346", // Abracon ABS07-32.768KHZ-T 32.768kHz
ESIM: "C5446401", // Murata SC20-FP MFF2 eSIM (or equivalent)
} as const
export default () => (
<board width="50mm" height="50mm">
{/* Re-center: child coordinates are authored in a 0..50 frame (top-left origin
as documented in CLAUDE.md placement table). The <board> centers at (0,0),
spanning -25..+25 in both axes. Translate the whole subtree by (-25,-25)
so authored coordinates land inside the board outline. Board grew from
40×40 to 50×50 to accommodate the 23.6×19.9mm BG95 LGA96 footprint
plus required courtyard clearance. */}
<group pcbX={-25} pcbY={-25}>
{/* ════════════════════════════════════════════════════════════════════
POWER PATH — VBUS / BAT_P / VSYS / _3V3 / _1V8
════════════════════════════════════════════════════════════════════ */}
{/* USB-C inlet (west edge) — power-only 6-pin */}
<chip
name="J1"
pcbX={4}
pcbY={28}
pcbRotation={90}
pinLabels={{
pin1: "GND",
pin2: "VBUS",
pin3: "CC1",
pin4: "DP",
pin5: "DM",
pin6: "CC2",
}}
footprint={usbcFootprint()}
connections={{
GND: "net.GND",
VBUS: "net.VBUS",
CC1: "net.USB_CC1",
DP: "net.USB_DP_RAW",
DM: "net.USB_DM_RAW",
CC2: "net.USB_CC2",
}}
/>
{/* USB-C CC1/CC2 5.1k pulldowns (sink role) */}
<resistor
name="R_CC1"
resistance="5.1k"
footprint="0402"
pcbX={12.5}
pcbY={28}
connections={{ pin1: "net.USB_CC1", pin2: "net.GND" }}
/>
<resistor
name="R_CC2"
resistance="5.1k"
footprint="0402"
pcbX={12.5}
pcbY={30}
connections={{ pin1: "net.USB_CC2", pin2: "net.GND" }}
/>
{/* USB ESD diode array (D+ / D- protection) — USBLC6-2SC6 / ESDA6V1-5SC6 */}
<chip
name="D1"
footprint="sot23-6"
pcbX={9}
pcbY={30}
pinLabels={{
pin1: "DP_HOST",
pin2: "GND",
pin3: "DM_HOST",
pin4: "DM_USB",
pin5: "VBUS_REF",
pin6: "DP_USB",
}}
connections={{
DP_HOST: "net.USB_DP",
GND: "net.GND",
DM_HOST: "net.USB_DM",
DM_USB: "net.USB_DM_RAW",
VBUS_REF: "net.VBUS",
DP_USB: "net.USB_DP_RAW",
}}
/>
{/* USB VBUS TVS — bidirectional 5V (clamp transients on VBUS rail) */}
<chip
name="U6"
footprint="sma"
pcbX={4}
pcbY={36}
pinLabels={{ pin1: "VBUS", pin2: "GND" }}
connections={{ VBUS: "net.VBUS", GND: "net.GND" }}
/>
{/* VBUS bulk decoupler */}
<capacitor
name="C_VBUS"
capacitance="4.7uF"
footprint="0402"
pcbX={8.1}
pcbY={33.5}
connections={{ pin1: "net.VBUS", pin2: "net.GND" }}
/>
{/* JST PH battery connector — pin 1=BAT_P_RAW, pin 2=GND */}
<chip
name="J2"
pcbX={47}
pcbY={30}
pcbRotation={270}
pinLabels={{ pin1: "BATPOS", pin2: "GND" }}
footprint={jstph2Footprint()}
connections={{ BATPOS: "net.BAT_P_RAW", GND: "net.GND" }}
/>
{/* Battery TVS — 5V bidirectional clamp on BAT_P_RAW */}
<chip
name="U7"
footprint="sma"
pcbX={46.5}
pcbY={26}
pinLabels={{ pin1: "BATPOS", pin2: "GND" }}
connections={{ BATPOS: "net.BAT_P_RAW", GND: "net.GND" }}
/>
{/* Reverse-polarity P-MOSFET on BAT_P_RAW → BAT_P (CLAUDE.md hard rule)
Source = BAT_P_RAW (battery side), Drain = BAT_P (system side),
Gate pulled to GND through 100k so FET conducts when battery polarity correct. */}
<chip
name="Q1"
footprint="sot23"
pcbX={47}
pcbY={37}
pinLabels={{ pin1: "GATE", pin2: "SOURCE", pin3: "DRAIN" }}
connections={{
GATE: "net.GND",
SOURCE: "net.BAT_P_RAW",
DRAIN: "net.BAT_P",
}}
/>
{/* Battery NTC thermistor (10k B=3380, BQ25180 TS sense) */}
<resistor
name="R8"
resistance="10k"
footprint="0402"
pcbX={43}
pcbY={34}
connections={{ pin1: "net.NTC_TS", pin2: "net.GND" }}
/>
{/* NTC pullup divider top leg from _3V3 */}
<resistor
name="R_NTC_PU"
resistance="10k"
footprint="0402"
pcbX={46.1}
pcbY={34}
connections={{ pin1: "net._3V3", pin2: "net.NTC_TS" }}
/>
{/* Battery decoupling caps */}
<capacitor
name="C_BAT"
capacitance="4.7uF"
footprint="0402"
pcbX={48}
pcbY={34}
connections={{ pin1: "net.BAT_P", pin2: "net.GND" }}
/>
{/* ────────────── BQ25180 linear charger (I2C 0x6A) ────────────── */}
{/* Pin map (WCSP9, per SLUSDP3):
1=IN 2=PMID 3=BAT 4=GND 5=SYS 6=SCL 7=TS 8=INT 9=SDA */}
<chip
name="U3"
pcbX={24}
pcbY={15}
pinLabels={{
pin1: "IN",
pin2: "PMID",
pin3: "BAT",
pin4: "GND",
pin5: "SYS",
pin6: "SCL",
pin7: "TS",
pin8: "INT",
pin9: "SDA",
}}
footprint={bq25180Footprint()}
connections={{
IN: "net.VBUS",
PMID: "net.PMID",
BAT: "net.BAT_P",
GND: "net.GND",
SYS: "net.VSYS",
SCL: "net.I2C_SCL",
TS: "net.NTC_TS",
INT: "net.CHG_INT",
SDA: "net.I2C_SDA",
}}
/>
{/* PMID cap (BQ25180 needs 1µF on PMID per datasheet) */}
<capacitor
name="C_PMID"
capacitance="4.7uF"
footprint="0402"
pcbX={20.9}
pcbY={15}
connections={{ pin1: "net.PMID", pin2: "net.GND" }}
/>
<capacitor
name="C_CHG_VIN"
capacitance="100nF"
footprint="0402"
pcbX={27.1}
pcbY={15}
connections={{ pin1: "net.VBUS", pin2: "net.GND" }}
/>
{/* ────────────── BQ51013B Qi wireless RX (I2C 0x6E) ────────────── */}
{/* Selected pin map (QFN28 RHL); inner-pin map per SLUSC11 */}
<chip
name="IC2"
pcbX={39}
pcbY={19}
pinLabels={{
pin1: "AC1",
pin2: "AC1B",
pin3: "BOOT1",
pin4: "RECT",
pin5: "CLAMP1",
pin6: "OUT",
pin7: "OUT2",
pin8: "FOD",
pin9: "TERM",
pin10: "ILIM",
pin11: "TS_CTRL",
pin12: "AD",
pin13: "AD_EN",
pin14: "EN1",
pin15: "EN2",
pin16: "COMM2",
pin17: "COMM1",
pin18: "CHG",
pin19: "PGND",
pin20: "PGND2",
pin21: "CLAMP2",
pin22: "RECT2",
pin23: "BOOT2",
pin24: "AC2B",
pin25: "AC2",
pin26: "SDA",
pin27: "SCL",
pin28: "INT",
pin29: "GND",
}}
footprint={bq51013Footprint()}
connections={{
AC1: "net.QI_AC1",
AC1B: "net.QI_AC1",
BOOT1: "net.QI_BOOT1",
RECT: "net.QI_VOUT",
CLAMP1: "net.QI_CLAMP1",
OUT: "net.QI_VOUT",
OUT2: "net.QI_VOUT",
FOD: "net.QI_FOD",
TERM: "net.QI_TERM",
ILIM: "net.QI_ILIM",
TS_CTRL: "net.QI_TS",
AD: "net.QI_AD",
AD_EN: "net.GND",
EN1: "net.GND",
EN2: "net._3V3",
COMM2: "net.QI_COMM2",
COMM1: "net.QI_COMM1",
CHG: "net.QI_CHG",
PGND: "net.GND",
PGND2: "net.GND",
CLAMP2: "net.QI_CLAMP2",
RECT2: "net.QI_VOUT",
BOOT2: "net.QI_BOOT2",
AC2B: "net.QI_AC2",
AC2: "net.QI_AC2",
SDA: "net.I2C_SDA",
SCL: "net.I2C_SCL",
INT: "net.QI_INT",
GND: "net.GND",
}}
/>
{/* Qi input/output caps */}
<capacitor name="C_QI_AC1" capacitance="22uF" footprint="0805" pcbX={44.6} pcbY={19} connections={{ pin1: "net.QI_AC1", pin2: "net.GND" }} />
<capacitor name="C_QI_AC2" capacitance="22uF" footprint="0805" pcbX={43.85} pcbY={21.8} connections={{ pin1: "net.QI_AC2", pin2: "net.GND" }} />
<capacitor name="C_QI_VOUT" capacitance="22uF" footprint="0805" pcbX={40.5} pcbY={27.0} connections={{ pin1: "net.QI_VOUT", pin2: "net.GND" }} />
<capacitor name="C_QI_BOOT1" capacitance="100nF" footprint="0402" pcbX={39} pcbY={24.6} connections={{ pin1: "net.QI_BOOT1", pin2: "net.QI_AC1" }} />
<capacitor name="C_QI_BOOT2" capacitance="100nF" footprint="0402" pcbX={36.2} pcbY={23.85} connections={{ pin1: "net.QI_BOOT2", pin2: "net.QI_AC2" }} />
<capacitor name="C_QI_CLAMP1" capacitance="100nF" footprint="0402" pcbX={34.15} pcbY={21.8} connections={{ pin1: "net.QI_CLAMP1", pin2: "net.GND" }} />
<capacitor name="C_QI_CLAMP2" capacitance="100nF" footprint="0402" pcbX={33.4} pcbY={19} connections={{ pin1: "net.QI_CLAMP2", pin2: "net.GND" }} />
{/* Qi config resistors */}
<resistor name="R_QI_FOD" resistance="100k" footprint="0402" pcbX={34.15} pcbY={16.2} connections={{ pin1: "net.QI_FOD", pin2: "net.GND" }} />
<resistor name="R_QI_TERM" resistance="10k" footprint="0402" pcbX={36.2} pcbY={14.15} connections={{ pin1: "net.QI_TERM", pin2: "net.GND" }} />
<resistor name="R_QI_ILIM" resistance="10k" footprint="0402" pcbX={39} pcbY={13.4} connections={{ pin1: "net.QI_ILIM", pin2: "net.GND" }} />
<resistor name="R_QI_TS" resistance="10k" footprint="0402" pcbX={41.8} pcbY={14.15} connections={{ pin1: "net.QI_TS", pin2: "net.GND" }} />
{/* QI_VOUT feeds VSYS (in parallel with USB charger SYS rail).
Tie via 0Ω jumper R_QI_OR for board-level OR-ing. */}
<resistor
name="R_QI_OR"
resistance="0"
footprint="0402"
pcbX={43.85}
pcbY={16.2}
connections={{ pin1: "net.QI_VOUT", pin2: "net.VSYS" }}
/>
{/* ────────────── BQ27220 fuel gauge (I2C 0x55) ────────────── */}
{/* DSBGA-12 ball map per SLUSCY9 */}
<chip
name="U5"
pcbX={27}
pcbY={6}
pinLabels={{
pin1: "GPOUT",
pin2: "BAT",
pin3: "BIN",
pin4: "SDA",
pin5: "SCL",
pin6: "SE",
pin7: "VSS",
pin8: "SRP",
pin9: "SRN",
pin10: "REGIN",
pin11: "BAT2",
pin12: "VCC",
}}
footprint={bq27220Footprint()}
connections={{
GPOUT: "net.FG_ALERT",
BAT: "net.BAT_FG_SENSE", // FIX iter-3: BAT/BAT2 pins ADC-sense via 1k series (R_FG_BAT) per SLUSCY9 §7.1 ESD protection
BIN: "net.BAT_P",
SDA: "net.I2C_SDA",
SCL: "net.I2C_SCL",
SE: "net._3V3",
VSS: "net.GND",
SRP: "net.BAT_P",
SRN: "net.GND",
REGIN: "net._3V3",
BAT2: "net.BAT_FG_SENSE", // shared with BAT pin behind same 1k series
VCC: "net._3V3",
}}
/>
<capacitor name="C_FG_VCC" capacitance="100nF" footprint="0402" pcbX={30.1} pcbY={6} connections={{ pin1: "net._3V3", pin2: "net.GND" }} />
{/* FIX iter-3: 1kΩ series resistor protects BQ27220 BAT/BAT2 ADC inputs from battery ESD events
per TI SLUSCY9 §7.1 application schematic. Was: BAT pins directly tied to BAT_P. */}
<resistor name="R_FG_BAT" resistance="1k" footprint="0402" pcbX={28.6} pcbY={4.4} connections={{ pin1: "net.BAT_P", pin2: "net.BAT_FG_SENSE" }} />
{/* ────────────── TPS62840 buck converter → _3V3 (=VSYS internally) ────────────── */}
{/* Pin map (X2SON-8 DSG): 1=VIN 2=EN 3=MODE 4=AGND 5=PGND 6=SW 7=FB 8=VOS */}
<chip
name="IC3"
pcbX={22}
pcbY={6}
pinLabels={{
pin1: "VIN",
pin2: "EN",
pin3: "MODE",
pin4: "AGND",
pin5: "PGND",
pin6: "SW",
pin7: "FB",
pin8: "VOS",
}}
footprint={tps62840Footprint()}
connections={{
VIN: "net.VSYS",
EN: "net.VSYS",
MODE: "net.GND",
AGND: "net.GND",
PGND: "net.GND",
SW: "net.SW_BUCK",
FB: "net.FB_BUCK",
VOS: "net._3V3",
}}
/>
<inductor
name="L1"
inductance="2.2uH"
footprint="0805"
pcbX={18}
pcbY={6}
connections={{ pin1: "net.SW_BUCK", pin2: "net._3V3" }}
/>
{/* Buck input cap */}
<capacitor name="C_BUCK_IN" capacitance="10uF" footprint="0603" pcbX={25.1} pcbY={6} connections={{ pin1: "net.VSYS", pin2: "net.GND" }} />
{/* Buck output cap */}
<capacitor name="C_BUCK_OUT" capacitance="10uF" footprint="0603" pcbX={22} pcbY={9.1} connections={{ pin1: "net._3V3", pin2: "net.GND" }} />
{/* FB divider sets 3.3V output: Vout = 0.6V × (1 + Rtop/Rbot)
Rtop=390k, Rbot=86.6k → Vout = 0.6 × (1 + 390/86.6) = 3.302V (exact target).
FIX iter-3: was Rbot=100k giving Vout=2.94V — fab-stopping bug caught by decoupling audit.
86.6kΩ is standard E96 1% (Uni-Royal 0402WGF8662TCE, LCSC C115175). */}
<resistor name="R_FB_TOP" resistance="390k" footprint="0402" pcbX={19.0} pcbY={8.5} connections={{ pin1: "net._3V3", pin2: "net.FB_BUCK" }} />
<resistor name="R_FB_BOT" resistance="86.6k" footprint="0402" pcbX={22} pcbY={2.9} connections={{ pin1: "net.FB_BUCK", pin2: "net.GND" }} />
{/* ────────────── TPS7A02 LDO → _1V8 analog rail ────────────── */}
{/* Pin map (X2SON-6 DQN): 1=IN 2=GND 3=NR 4=NC 5=EN 6=OUT */}
<chip
name="U4"
pcbX={26}
pcbY={11}
pinLabels={{
pin1: "IN",
pin2: "GND",
pin3: "NR",
pin4: "NC",
pin5: "EN",
pin6: "OUT",
}}
footprint={tps7a02Footprint()}
connections={{
IN: "net._3V3",
GND: "net.GND",
NR: "net.LDO_NR",
NC: "net.LDO_NC",
EN: "net._3V3",
OUT: "net._1V8",
}}
/>
<capacitor name="C_LDO_IN" capacitance="100nF" footprint="0402" pcbX={28.6} pcbY={11} connections={{ pin1: "net._3V3", pin2: "net.GND" }} />
<capacitor name="C_LDO_OUT" capacitance="100nF" footprint="0402" pcbX={24.7} pcbY={13.25} connections={{ pin1: "net._1V8", pin2: "net.GND" }} />
<capacitor name="C_LDO_NR" capacitance="10nF" footprint="0402" pcbX={24.7} pcbY={8.75} connections={{ pin1: "net.LDO_NR", pin2: "net.GND" }} />
{/* VSYS bulk tantalum (C21 per CLAUDE.md placement table) */}
<capacitor
name="C21"
capacitance="10uF"
footprint="1210"
pcbX={32.0}
pcbY={13.0}
connections={{ pin1: "net.VSYS", pin2: "net.GND" }}
/>
{/* ════════════════════════════════════════════════════════════════════
DIGITAL CORE — nRF52840, crystals (continued in part B)
════════════════════════════════════════════════════════════════════ */}
{/* ════════════════════════════════════════════════════════════════════
PART B — DIGITAL CORE + SENSORS + RADIOS
════════════════════════════════════════════════════════════════════ */}
{/* ────────────── nRF52840 MCU (IC1) ────────────────────────────────
QFN73 7×7mm, 0.5mm pitch.
Pin assignments (QFN73 per Nordic PS v1.7 Table 4):
Pin 1 = VDD → _3V3
Pin 2 = P0.00/XL1 → LFXO (32kHz XIN) — reserved
Pin 3 = P0.01/XL2 → LFXO (32kHz XOUT) — reserved
Pin 4 = P0.02 → MODEM_RESET_N
Pin 5 = P0.03 → MODEM_PWRKEY
Pin 6 = P0.04 → IMU_INT
Pin 7 = P0.05/AIN3 → MODEM_DTR
Pin 8 = GND
Pin 9 = P0.06 → CHG_INT (BQ25180 INT)
Pin 10 = P0.07 → FG_ALERT (BQ27220 GPOUT)
Pin 11 = P0.08 → QI_INT
Pin 12 = P0.09 → nc (spare)
Pin 13 = P0.10 → nc (spare)
Pin 14 = P0.11 → nc (spare)
Pin 15 = P0.12 → nc (spare)
Pin 16 = P0.13 → nc (spare)
Pin 17 = USBD_DM → USB_DM
Pin 18 = USBD_DP → USB_DP
Pin 19 = VBUS_DETECT/P0.14 → nc (VBUS detect — optional)
Pin 20 = P0.15 → nc (spare)
Pins 21-36 (right column):
Pin 21 = P0.16 → nc
Pin 22 = P0.17 → nc
Pin 23 = P0.18 → nc
Pin 24 = P0.19 → nc
Pin 25 = P0.20 → nc
Pin 26 = P0.21 → nc
Pin 27 = P0.22 → nc
Pin 28 = P0.23 → nc
Pin 29 = VDDHDMI (no-connect in non-NFC use)
Pin 30 = P0.24 → nc
Pin 31 = P0.25 → nc
Pin 32 = P0.26 → nc
Pin 33 = P0.27 → nc
Pin 34 = GND
Pin 35 = DCCH/DCC → decouple 100nF to GND
Pin 36 = VDD → _3V3
Pins 37-56 (top row, right→left):
Pin 37 = P0.28/AIN4 → I2C_SCL
Pin 38 = P0.29/AIN5 → I2C_SDA
Pin 39 = P0.30/AIN6 → MODEM_RX (nRF RX ← modem TX)
Pin 40 = P0.31/AIN7 → MODEM_TX (nRF TX → modem RX)
Pin 41 = GND
Pin 42 = AVDD → _3V3 (0.1µF bypass)
Pin 43 = P1.00/TRACEDATA0 → nc
Pin 44 = P1.01/TRACECLK → nc
Pin 45 = P1.02 → nc
Pin 46 = P1.03 → nc
Pin 47 = P1.04 → nc
Pin 48 = P1.05 → nc
Pin 49 = P1.06 → nc
Pin 50 = P1.07 → nc
Pin 51 = P1.08 → nc
Pin 52 = P1.09 → nc
Pin 53 = P1.10 → nc
Pin 54 = P1.11 → nc
Pin 55 = P1.12 → nc
Pin 56 = P1.13 → nc
Pins 57-72 (left column, top→bottom):
Pin 57 = P1.14 → nc
Pin 58 = P1.15 → nc
Pin 59 = GND
Pin 60 = VDD → _3V3
Pin 61 = DEC1 → decouple 100nF to GND
Pin 62 = DEC2 → decouple 100nF to GND
Pin 63 = DEC3 → decouple 100nF to GND
Pin 64 = DEC4 → decouple 100nF to GND
Pin 65 = VDD → _3V3
Pin 66 = GND
Pin 67 = SWDIO → SWDIO (programming)
Pin 68 = SWDCLK → SWDCLK (programming)
Pin 69 = GND
Pin 70 = RESET_N → MCU_NRST (10k pullup to _3V3)
Pin 71 = GND
Pin 72 = XC1 (32MHz HFXO) → HFXO_XIN
Pin 73 = XC2 / EP → HFXO_XOUT / GND thermal pad
──────────────────────────────────────────────────────────────────── */}
<chip
name="IC1"
pcbX={11}
pcbY={17}
pinLabels={{
pin1: "VDD",
pin2: "XL1",
pin3: "XL2",
pin4: "MODEM_RESET_N",
pin5: "MODEM_PWRKEY",
pin6: "IMU_INT",
pin7: "MODEM_DTR",
pin8: "GND",
pin9: "CHG_INT_IN",
pin10: "FG_ALERT_IN",
pin11: "QI_INT_IN",
pin12: "NC12",
pin13: "NC13",
pin14: "NC14",
pin15: "NC15",
pin16: "NC16",
pin17: "USBD_DM",
pin18: "USBD_DP",
pin19: "VBUS_DETECT",
pin20: "NC20",
pin21: "NC21",
pin22: "NC22",
pin23: "NC23",
pin24: "NC24",
pin25: "NC25",
pin26: "NC26",
pin27: "NC27",
pin28: "NC28",
pin29: "VDDHDMI",
pin30: "NC30",
pin31: "NC31",
pin32: "NC32",
pin33: "NC33",
pin34: "GND34",
pin35: "DCCH",
pin36: "VDD36",
pin37: "SCL",
pin38: "SDA",
pin39: "MODEM_RX",
pin40: "MODEM_TX",
pin41: "GND41",
pin42: "AVDD",
pin43: "NC43",
pin44: "NC44",
pin45: "NC45",
pin46: "NC46",
pin47: "NC47",
pin48: "NC48",
pin49: "NC49",
pin50: "NC50",
pin51: "NC51",
pin52: "NC52",
pin53: "NC53",
pin54: "NC54",
pin55: "NC55",
pin56: "NC56",
pin57: "NC57",
pin58: "NC58",
pin59: "GND59",
pin60: "VDD60",
pin61: "DEC1",
pin62: "DEC2",
pin63: "DEC3",
pin64: "DEC4",
pin65: "VDD65",
pin66: "GND66",
pin67: "SWDIO",
pin68: "SWDCLK",
pin69: "GND69",
pin70: "RESET_N",
pin71: "GND71",
pin72: "XC1",
pin73: "EP",
}}
footprint={nrf52840Footprint()}
connections={{
// Power
VDD: "net._3V3",
VDD36: "net._3V3",
VDD60: "net._3V3",
VDD65: "net._3V3",
AVDD: "net._3V3",
VDDHDMI: "net._3V3",
GND: "net.GND",
GND34: "net.GND",
GND41: "net.GND",
GND59: "net.GND",
GND66: "net.GND",
GND69: "net.GND",
GND71: "net.GND",
EP: "net.GND",
// Decoupling pins (connected externally via caps)
DEC1: "net.MCU_DEC1",
DEC2: "net.MCU_DEC2",
DEC3: "net.MCU_DEC3",
DEC4: "net.MCU_DEC4",
DCCH: "net.MCU_DCCH",
// 32kHz LFXO crystal — P0.00/XL1, P0.01/XL2
XL1: "net.LFXO_XIN",
XL2: "net.LFXO_XOUT",
// 32MHz HFXO crystal
XC1: "net.HFXO_XIN",
// SWD debug
SWDIO: "net.SWDIO",
SWDCLK: "net.SWDCLK",
RESET_N: "net.MCU_NRST",
// USB
USBD_DM: "net.USB_DM",
USBD_DP: "net.USB_DP",
VBUS_DETECT: "net.VBUS",
// I2C bus (shared: BQ25180 0x6A, BQ27220 0x55, BQ51013 0x6E, BNO086 0x4A)
SDA: "net.I2C_SDA",
SCL: "net.I2C_SCL",
// UART to BG95 modem (v1 bug fix: TX≠IMU_CS — use P0.31/P0.30)
MODEM_TX: "net.MODEM_TX",
MODEM_RX: "net.MODEM_RX",
// Modem control GPIOs
MODEM_PWRKEY: "net.MODEM_PWRKEY",
MODEM_RESET_N:"net.MODEM_RESET_N",
MODEM_DTR: "net.MODEM_DTR",
// Interrupt inputs
IMU_INT: "net.IMU_INT",
CHG_INT_IN: "net.CHG_INT",
FG_ALERT_IN: "net.FG_ALERT",
QI_INT_IN: "net.QI_INT",
// Unconnected
NC12: "net.MCU_NC",
NC13: "net.MCU_NC",
NC14: "net.MCU_NC",
NC15: "net.MCU_NC",
NC16: "net.MCU_NC",
NC20: "net.MCU_NC",
NC21: "net.MCU_NC",
NC22: "net.MCU_NC",
NC23: "net.MCU_NC",
NC24: "net.MCU_NC",
NC25: "net.MCU_NC",
NC26: "net.MCU_NC",
NC27: "net.MCU_NC",
NC28: "net.MCU_NC",
NC30: "net.MCU_NC",
NC31: "net.MCU_NC",
NC32: "net.MCU_NC",
NC33: "net.MCU_NC",
NC43: "net.MCU_NC",
NC44: "net.MCU_NC",
NC45: "net.MCU_NC",
NC46: "net.MCU_NC",
NC47: "net.MCU_NC",
NC48: "net.MCU_NC",
NC49: "net.MCU_NC",
NC50: "net.MCU_NC",
NC51: "net.MCU_NC",
NC52: "net.MCU_NC",
NC53: "net.MCU_NC",
NC54: "net.MCU_NC",
NC55: "net.MCU_NC",
NC56: "net.MCU_NC",
NC57: "net.MCU_NC",
NC58: "net.MCU_NC",
}}
/>
{/* nRF52840 VDD/AVDD bulk + local decoupling caps
Per nRF52840 PS §4.3: 100nF on each DEC pin, 1µF on AVDD. */}
<capacitor name="C_MCU_VDD" capacitance="100nF" footprint="0402" pcbX={18.1} pcbY={17} connections={{ pin1: "net._3V3", pin2: "net.GND" }} />
<capacitor name="C_MCU_AVDD" capacitance="100nF" footprint="0402" pcbX={17.5} pcbY={22.0} connections={{ pin1: "net._3V3", pin2: "net.GND" }} />
<capacitor name="C_MCU_DEC1" capacitance="100nF" footprint="0402" pcbX={13.19} pcbY={23.75} connections={{ pin1: "net.MCU_DEC1", pin2: "net.GND" }} />
<capacitor name="C_MCU_DEC2" capacitance="100nF" footprint="0402" pcbX={8.81} pcbY={23.75} connections={{ pin1: "net.MCU_DEC2", pin2: "net.GND" }} />
<capacitor name="C_MCU_DEC3" capacitance="100nF" footprint="0402" pcbX={8.5} pcbY={27.0} connections={{ pin1: "net.MCU_DEC3", pin2: "net.GND" }} />
<capacitor name="C_MCU_DEC4" capacitance="100nF" footprint="0402" pcbX={3.9} pcbY={17} connections={{ pin1: "net.MCU_DEC4", pin2: "net.GND" }} />
<capacitor name="C_MCU_DCCH" capacitance="100nF" footprint="0402" pcbX={5.26} pcbY={9.5} connections={{ pin1: "net.MCU_DCCH", pin2: "net.GND" }} />
{/* MCU NRST 10k pullup */}
<resistor name="R_MCU_RST" resistance="10k" footprint="0402" pcbX={8.81} pcbY={10.25} connections={{ pin1: "net._3V3", pin2: "net.MCU_NRST" }} />
{/* ────────────── I2C bus pullups (shared bus: BQ25180/BQ27220/BQ51013/BNO086) ── */}
<resistor
name="R_SDA"
resistance="4.7k"
footprint="0402"
pcbX={13.19}
pcbY={10.25}
connections={{ pin1: "net._3V3", pin2: "net.I2C_SDA" }}
/>
<resistor
name="R_SCL"
resistance="4.7k"
footprint="0402"
pcbX={16.74}
pcbY={11.0}
connections={{ pin1: "net._3V3", pin2: "net.I2C_SCL" }}
/>
{/* ────────────── 32MHz HFXO crystal (X1) ───────────────────────────
Abracon ABM8-272-T3 (LCSC C383439), 12pF load caps within 2mm.
HFXO_XIN connects to nRF52840 XC1 (pin 72), HFXO_XOUT to EP/GND side.
⚠️ CLAUDE.md: load caps <2mm from X1, traces <5mm. ─────────────── */}
<chip
name="X1"
footprint={crystalHfxoFootprint()}
pcbX={4}
pcbY={22}
pinLabels={{
pin1: "XIN",
pin2: "GND",
pin3: "XOUT",
pin4: "GND2",
}}
connections={{
XIN: "net.HFXO_XIN",
GND: "net.GND",
XOUT: "net.HFXO_XOUT",
GND2: "net.GND",
}}
/>
{/* 12pF load caps — must be within 2mm of X1 per CLAUDE.md hard rule */}
<capacitor name="C_HFXO1" capacitance="12pF" footprint="0402" pcbX={7.6} pcbY={22} connections={{ pin1: "net.HFXO_XIN", pin2: "net.GND" }} />
<capacitor name="C_HFXO2" capacitance="12pF" footprint="0402" pcbX={1.4} pcbY={22} connections={{ pin1: "net.HFXO_XOUT", pin2: "net.GND" }} />
{/* ────────────── 32.768kHz LFXO crystal (Y1) ───────────────────────
Abracon ABS07-32.768KHZ-T (LCSC C32346), 12.5pF load caps.
LFXO_XIN → nRF52840 XL1 (P0.00/pin 2), LFXO_XOUT → XL2 (P0.01/pin 3). ─── */}
<chip
name="Y1"
footprint={crystalLfxoFootprint()}
pcbX={4}
pcbY={12}
pinLabels={{
pin1: "XIN",
pin2: "XOUT",
}}
connections={{
XIN: "net.LFXO_XIN",
XOUT: "net.LFXO_XOUT",
}}
/>
{/* 12pF LFXO load caps */}
<capacitor name="C_LFXO1" capacitance="12pF" footprint="0402" pcbX={7.6} pcbY={12} connections={{ pin1: "net.LFXO_XIN", pin2: "net.GND" }} />
<capacitor name="C_LFXO2" capacitance="12pF" footprint="0402" pcbX={1.4} pcbY={12} connections={{ pin1: "net.LFXO_XOUT", pin2: "net.GND" }} />
{/* ────────────── BNO086 IMU (U1) — I2C 0x4A (ADR=GND) ─────────────
LGA-28 3.2×3.8mm, 28 pads (4×7 grid).
Key pin map (per BNO086 datasheet Table 5-2):
pin1=GND, pin2=RSTB (active-low reset), pin3=GND,
pin4=BOOTN (BOOT mode sel, pull high for normal), pin5=INTN (active-low INT),
pin6=GND, pin7=VDDIO (1.8V I/O supply),
pin8=SDA, pin9=SCL, pin10=GND, pin11=ADR (I2C addr sel: GND→0x4A),
pin12=GND, pin13=GND, pin14=GPIO0, pin15=GPIO1,
pin16=GND, pin17=GND, pin18=GND,
pin19=VDD (3.3V core), pin20=GND,
pin21=GND, pin22=GND, pin23=GND,
pin24=GND, pin25=GND, pin26=GND, pin27=GND, pin28=GND
──────────────────────────────────────────────────────────────────── */}
<chip
name="U1"
pcbX={11}
pcbY={6}
pinLabels={{
pin1: "GND1",
pin2: "RSTB",
pin3: "GND3",
pin4: "BOOTN",
pin5: "INTN",
pin6: "GND6",
pin7: "VDDIO",
pin8: "SDA",
pin9: "SCL",
pin10: "GND10",
pin11: "ADR",
pin12: "GND12",
pin13: "GND13",
pin14: "GPIO0",
pin15: "GPIO1",
pin16: "GND16",
pin17: "GND17",
pin18: "GND18",
pin19: "VDD",
pin20: "GND20",
pin21: "GND21",
pin22: "GND22",
pin23: "GND23",
pin24: "GND24",
pin25: "GND25",
pin26: "GND26",
pin27: "GND27",
pin28: "GND28",
}}
footprint={bno086Footprint()}
connections={{
GND1: "net.GND",
RSTB: "net._3V3", // held high; MCU can drive low via open-drain if needed
GND3: "net.GND",
BOOTN: "net._3V3", // normal boot (not DFU)
INTN: "net.IMU_INT", // → IC1 pin6 (P0.04)
GND6: "net.GND",
VDDIO: "net._1V8", // 1.8V I/O from TPS7A02
SDA: "net.I2C_SDA",
SCL: "net.I2C_SCL",
GND10: "net.GND",
ADR: "net.GND", // ADR=GND → I2C addr 0x4A ✓
GND12: "net.GND",
GND13: "net.GND",
GPIO0: "net.GND",
GPIO1: "net.GND",
GND16: "net.GND",
GND17: "net.GND",
GND18: "net.GND",
VDD: "net._3V3", // 3.3V core supply
GND20: "net.GND",
GND21: "net.GND",
GND22: "net.GND",
GND23: "net.GND",
GND24: "net.GND",
GND25: "net.GND",
GND26: "net.GND",
GND27: "net.GND",
GND28: "net.GND",
}}
/>
{/* BNO086 supply decoupling */}
<capacitor name="C_IMU_VDD" capacitance="100nF" footprint="0402" pcbX={16.1} pcbY={4} connections={{ pin1: "net._3V3", pin2: "net.GND" }} />
<capacitor name="C_IMU_VDDIO" capacitance="100nF" footprint="0402" pcbX={5.9} pcbY={6} connections={{ pin1: "net._1V8", pin2: "net.GND" }} />
{/* ────────────── BG95-M3 modem (U2) ────────────────────────────────
LGA-96 23.6×19.9mm, placed at (20,30) — north zone per CLAUDE.md.
⚠️ Antenna: 5mm keepout around antenna pads. No traces under module.
Simplified pad assignments (Quectel BG95 HW Design §3.2):
pin1=GND, pin2=VDD_EXT(1.8V out), pin3=STATUS, pin4=W_DISABLE_N,
pin5=PWRKEY, pin6=RESET_N, pin7=GND, pin8=GND,
pin9=UART_TX, pin10=UART_RX, pin11=GND, pin12=GND,
pin13=USIM_VCC, pin14=USIM_DATA, pin15=USIM_CLK,
pin16=USIM_RST, pin17=GND, pin18=VBAT, ... (GND pads fill rest)
Inner pads (50-59 in footprint): VBAT rails
──────────────────────────────────────────────────────────────────── */}
<chip
name="U2"
pcbX={18}
pcbY={36}
pinLabels={{
pin1: "GND1",
pin2: "VDD_EXT",
pin3: "STATUS",
pin4: "W_DISABLE_N",
pin5: "PWRKEY",
pin6: "RESET_N",
pin7: "GND7",
pin8: "GND8",
pin9: "UART_TX",
pin10: "UART_RX",
pin11: "GND11",
pin12: "GND12",
pin13: "USIM_VCC",
pin14: "USIM_DATA",
pin15: "USIM_CLK",
pin16: "USIM_RST",
pin17: "GND17",
pin18: "VBAT",
pin19: "GND19",
pin20: "GND20",
pin21: "GND21",
pin22: "GND22",
pin23: "GND23",
pin24: "GND24",
pin25: "GND25",
pin26: "GND26",
pin27: "GND27",
pin28: "GND28",
pin29: "GND29",
pin30: "GND30",
pin31: "GND31",
pin32: "GND32",
pin33: "GND33",
pin34: "GND34",
pin35: "GND35",
pin36: "GND36",
pin37: "GND37",
pin38: "GND38",
pin39: "GND39",
pin40: "GND40",
pin41: "GND41",
pin42: "GND42",
pin50: "VBAT50",
pin51: "VBAT51",
pin52: "VBAT52",
pin53: "VBAT53",
pin54: "VBAT54",
pin55: "GND55",
pin56: "GND56",
pin57: "GND57",
pin58: "GND58",
pin59: "GND59",
}}
footprint={bg95Footprint()}
connections={{
GND1: "net.GND",
VDD_EXT: "net.MODEM_VDD_EXT", // 1.8V aux out — not connected to MCU
STATUS: "net.GND", // optional status monitor, tie low
W_DISABLE_N:"net._3V3", // pull high → RF always enabled
PWRKEY: "net.MODEM_PWRKEY", // → IC1 pin5 (P0.03)
RESET_N: "net.MODEM_RESET_N", // → IC1 pin4 (P0.02)
GND7: "net.GND",
GND8: "net.GND",
UART_TX: "net.MODEM_TX", // modem TX → nRF RX (P0.30)
UART_RX: "net.MODEM_RX", // modem RX ← nRF TX (P0.31)
GND11: "net.GND",
GND12: "net.GND",
USIM_VCC: "net.ESIM_VCC",
USIM_DATA: "net.ESIM_DATA",
USIM_CLK: "net.ESIM_CLK",
USIM_RST: "net.ESIM_RST",
GND17: "net.GND",
VBAT: "net.BAT_P", // modem powered from battery rail
GND19: "net.GND", GND20: "net.GND", GND21: "net.GND",
GND22: "net.GND", GND23: "net.GND", GND24: "net.GND",
GND25: "net.GND", GND26: "net.GND", GND27: "net.GND",
GND28: "net.GND", GND29: "net.GND", GND30: "net.GND",
GND31: "net.GND", GND32: "net.GND", GND33: "net.GND",
GND34: "net.GND", GND35: "net.GND", GND36: "net.GND",
GND37: "net.GND", GND38: "net.GND", GND39: "net.GND",
GND40: "net.GND", GND41: "net.GND", GND42: "net.GND",
VBAT50: "net.BAT_P", VBAT51: "net.BAT_P", VBAT52: "net.BAT_P",
VBAT53: "net.BAT_P", VBAT54: "net.BAT_P",
GND55: "net.GND", GND56: "net.GND", GND57: "net.GND",
GND58: "net.GND", GND59: "net.GND",
}}
/>
{/* BG95 VBAT bulk decoupling (100µF + 4.7µF recommended by Quectel HW guide) */}
<capacitor name="C_BG95_BAT1" capacitance="4.7uF" footprint="0402" pcbX={32.1} pcbY={36} connections={{ pin1: "net.BAT_P", pin2: "net.GND" }} />
<capacitor name="C_BG95_BAT2" capacitance="4.7uF" footprint="0402" pcbX={18} pcbY={48} connections={{ pin1: "net.BAT_P", pin2: "net.GND" }} />
<capacitor name="C_BG95_BAT3" capacitance="10uF" footprint="0603" pcbX={3.9} pcbY={39.5} connections={{ pin1: "net.BAT_P", pin2: "net.GND" }} />
<capacitor name="C_BG95_UART" capacitance="100nF" footprint="0402" pcbX={21.5} pcbY={21.9} connections={{ pin1: "net._3V3", pin2: "net.GND" }} />
{/* ────────────── eSIM (U8) — MFF2 Murata SC20-FP ───────────────────
ETSI MFF2 6-contact footprint (5×6mm body).
Pin1=VCC, Pin2=RST, Pin3=CLK, Pin4=GND, Pin5=VPP, Pin6=I/O
Ties directly to BG95 USIM_* signals. VPP=NC (not used in LTE-M).
──────────────────────────────────────────────────────────────────── */}
<chip
name="U8"
pcbX={38}
pcbY={36}
pinLabels={{
pin1: "VCC",
pin2: "RST",
pin3: "CLK",
pin4: "GND",
pin5: "VPP",
pin6: "IO",
}}
footprint={esimFootprint()}
connections={{
VCC: "net.ESIM_VCC",
RST: "net.ESIM_RST",
CLK: "net.ESIM_CLK",
GND: "net.GND",
VPP: "net.GND", // VPP not used in 3GPP LTE-M / NB-IoT
IO: "net.ESIM_DATA",
}}
/>
{/* eSIM VCC decoupling — 100nF as close to U8 as possible */}
<capacitor name="C_ESIM_VCC" capacitance="100nF" footprint="0402" pcbX={43.6} pcbY={36} connections={{ pin1: "net.ESIM_VCC", pin2: "net.GND" }} />
{/* ════════════════════════════════════════════════════════════════════
GROUND POURS — top + bottom GND fill (return paths, shielding, EMI)
boardEdgeMargin=1.5mm doubles as the IP68 over-mold keepout (no copper
within 1.5mm of edge so potting bonds to bare FR-4).
════════════════════════════════════════════════════════════════════ */}
<copperpour name="GP_TOP" layer="top" connectsTo="net.GND" boardEdgeMargin="1.5mm" clearance="0.2mm" />
<copperpour name="GP_BOTTOM" layer="bottom" connectsTo="net.GND" boardEdgeMargin="1.5mm" clearance="0.2mm" />
{/* ════════════════════════════════════════════════════════════════════
KEEPOUTS — RF antenna clear zone + IP68 over-mold ring
════════════════════════════════════════════════════════════════════ */}
{/* BG95 antenna keepout: 5mm radius around antenna pin (north of U2).
Quectel BG95 HW Design §5.1 requires no copper / no traces under or
near MAIN_ANT pad. U2 center=(18,36); antenna pin is at the module's
north edge; 5mm radius around (18,46) covers the antenna trace zone. */}
<keepout shape="circle" radius="5mm" pcbX={18} pcbY={46} />
{/* IP68 over-mold ring: 1.5mm strip along all 4 board edges so the
TPU/silicone potting can grip bare FR-4 around the perimeter without
any copper leaching contact. Authored frame is 0..50 (group offset -25,-25). */}
<keepout shape="rect" pcbX={25} pcbY={49.25} width="50mm" height="1.5mm" />
<keepout shape="rect" pcbX={25} pcbY={0.75} width="50mm" height="1.5mm" />
<keepout shape="rect" pcbX={0.75} pcbY={25} width="1.5mm" height="50mm" />
<keepout shape="rect" pcbX={49.25} pcbY={25} width="1.5mm" height="50mm" />
{/* ════════════════════════════════════════════════════════════════════
RF ANTENNA FEED — BG95 MAIN_ANT → π-network → Antenova SR4L054
Signal flow (shared net naming, connections-prop style):
net.RF_NODE_A (BG95 antenna pad) →
L_ANT_S (series 2.7nH) →
net.RF_NODE_B (junction: shunt C_ANT_SH to GND) →
L_ANT_S2 (series 2.7nH) →
net.ANT_FEED → ANT1.FEED
Placement rationale:
U2 LGA96 (23.6×19.9mm) center=(18,36) → north edge y≈45.95.
Components placed at y=46.3–48.0, x=21–23 to clear:
- U2 footprint boundary (y<45.95)
- C_BG95_BAT2 at (18,48)
- IP68 north keepout (y>48.5)
BG95 has no discrete ANT pin in this footprint model; RF_NODE_A
is the intended feedpoint net for the BG95 antenna pad (MAIN_ANT).
Reference: Antenova SR4L054 datasheet pp.6-8; Quectel BG95 HW §5.1.
════════════════════════════════════════════════════════════════════ */}
{/* π-match series element 1 — 2.7nH 0402 (RF feedline between BG95 ant pad and shunt junction) */}
<inductor
name="L_ANT_S"
inductance="2.7nH"
footprint="0402"
pcbX={21}
pcbY={46.3}
connections={{ pin1: "net.RF_NODE_A", pin2: "net.RF_NODE_B" }}
/>
{/* π-match shunt element — 1.5pF 0402 (shunt to GND at junction between the two series inductors) */}
<capacitor
name="C_ANT_SH"
capacitance="1.5pF"
footprint="0402"
pcbX={23}
pcbY={46.3}
connections={{ pin1: "net.RF_NODE_B", pin2: "net.GND" }}
/>
{/* π-match series element 2 — 2.7nH 0402 (RF feedline from junction to chip antenna) */}
<inductor
name="L_ANT_S2"
inductance="2.7nH"
footprint="0402"
pcbX={21}
pcbY={47.1}
connections={{ pin1: "net.RF_NODE_B", pin2: "net.ANT_FEED" }}
/>
{/* Antenova SR4L054 chip antenna — 0805 body, pre-tuned LTE-M/NB-IoT.
JLCPCB part C2845812. Pin1=FEED, Pin2=GND. Placed north of π-match,
east of C_BG95_BAT2 (18,48) to avoid collision. */}
<chip
name="ANT1"
footprint="0805"
pcbX={22}
pcbY={48.0}
pinLabels={{ "1": "FEED", "2": "GND" }}
connections={{
FEED: "net.ANT_FEED",
GND: "net.GND",
}}
/>
{/* ════════════════════════════════════════════════════════════════════
GROUND STITCHING VIAS — antenna feed return path continuity
All vias are outside U2 footprint (x<6.2 or x>29.8 or y>45.95)
and outside IP68 north keepout (y<48.5).
Keepout circle (18,46) r=5mm is a copper-pour exclusion, not a
component exclusion — vias in the antenna zone are intentional.
Via spec: 0.3mm hole / 0.6mm pad (micro-via capable on JLCPCB).
════════════════════════════════════════════════════════════════════ */}
{/* West column of BG95 — outside footprint (x=5 < 6.2) */}
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={5} pcbY={37} connectsTo="net.GND" />
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={5} pcbY={40} connectsTo="net.GND" />
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={5} pcbY={43} connectsTo="net.GND" />
{/* East column of BG95 — outside footprint (x=31 > 29.8) */}
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={31} pcbY={37} connectsTo="net.GND" />
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={31} pcbY={40} connectsTo="net.GND" />
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={31} pcbY={43} connectsTo="net.GND" />
{/* North antenna feed zone — outside keepout circle (18,46) r=5; x=12 and x=24 give dist≈6.1 */}
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={12} pcbY={47} connectsTo="net.GND" />
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={24} pcbY={47} connectsTo="net.GND" />
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={12} pcbY={48.2} connectsTo="net.GND" />
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={24} pcbY={48.2} connectsTo="net.GND" />
{/* BG95 south-edge return path (y=25.5, just below U2 footprint south edge y≈26.05) */}
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={14} pcbY={25.5} connectsTo="net.GND" />
<via fromLayer="top" toLayer="bottom" holeDiameter="0.3mm" outerDiameter="0.6mm" pcbX={22} pcbY={25.5} connectsTo="net.GND" />
</group>
</board>
)
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