pixalynx/pixal-nfc-card

fabrication/rev-b/manufacturing-audit.log

PCB

Schematic

WARN `--no-project` was provided, but no project was found
Smallest top copper clearances (distinct source nets): [(0.17500000000000068, 'U1.NC1', 'pcb_trace_1'), (0.17500000000000068, 'U1.NC1', 'pcb_trace_2'), (0.20000000000000104, 'U1.NC1', 'U1.AC0'), (0.20000000000000104, 'U1.NC1', 'U1.AC1'), (0.20000000000000104, 'U1.NC1', 'U1.NC2'), (0.20000000000000104, 'U1.NC1', 'U1.NC3'), (0.39999999999999997, 'U1.AC1', 'U1.AC0'), (0.39999999999999997, 'U1.NC2', 'U1.NC3')]
Independent minimum turn clearance: (0.44999999999999846, 6, 9)
Coil centerline length mm: 829.5
Full-outline coil edge clearance mm: 3.275
Estimated coil DC resistance ohm at 35um copper: 0.9079733333333334
Approximate square current-sheet cross-check uH: 2.5362897220740117
f0 MHz, 2.536uH, C pF 47.5 14.50102503163687
f0 MHz, 2.536uH, C pF 50 14.13385087722915
f0 MHz, 2.536uH, C pF 52.5 13.793226102131614
f0 MHz, 2.536uH, C pF 55 13.476098053413988
f0 MHz, 2.536uH, C pF 60 12.902381583120976
Capacitance pF at 13.56MHz, 2.536uH: 54.32148514516253
F_Cu primitives 15 bounds (1.7999999999999998, -3.4, 13.999999999999998, 3.4) islands 5
B_Cu primitives 23 bounds (-39.525, -22.225, 7.1, 22.225) islands 1
F_Mask primitives 7 bounds (1.7999999999999998, -3.4, 13.999999999999998, 3.4) islands 7
B_Mask primitives 2 bounds (1.7999999999999998, -3.4, 7.1, 3.4) islands 2
F_Paste primitives 5 bounds (13.0, -0.8, 13.999999999999998, 0.8) islands 5
B_Paste primitives 0 bounds (nan, nan, nan, nan) islands 0
F_SilkScreen primitives 737 bounds (-40.449999999999996, -23.15, 40.1, 23.15) islands 174
Edge_Cuts primitives 204 bounds (-42.824999999999996, -27.025, 42.824999999999996, 27.025) islands 1
Silkscreen-mask minimum gap 0.4499999999999993 intersection area 0.0
Silkscreen line widths: [0.15, 0.153, 0.162, 0.2, 0.288, 0.3, 0.55, 0.6]
Silk clearance U1.NC1 0.6551
Silk clearance U1.NC2 1.4817
Silk clearance U1.AC1 1.7163
Silk clearance U1.AC0 0.9354
Silk clearance U1.NC3 0.4903
PASS two layers, 0.6 mm board
PASS 85.6 x 54 mm outline
PASS unrelated copper clearance >=0.15 mm
PASS every nonadjacent antenna turn separated
PASS rounded-outline antenna clearance
PASS five top paste apertures; zero bottom paste
PASS silkscreen to solder mask openings >=0.15 mm
PASS minimum silkscreen stroke 0.15 mm
PASS all silk at least 0.2 mm inside outline
PASS all pads and feeds inside routed edge clearance
PASS explicit both-layer RF keepout
PASS only IC and printed antenna exist
PASS exactly two feeds and one antenna trace
PASS no extra vias or copper fill
PASS RF keepout contains only allowed feed/terminal copper
PASS RF keepout contains only allowed feed/terminal copper
PASS RF keepout contains only allowed feed/terminal copper
PASS RF keepout contains only allowed feed/terminal copper
PASS F_Cu agrees with source copper (difference 0.00000000 mm2)
PASS bottom continuous coil / top two feeds plus three isolated NC pads
PASS B_Cu agrees with source copper (difference 0.00000000 mm2)
PASS bottom continuous coil / top two feeds plus three isolated NC pads
PASS IC paste 1:1 with manufacturer copper land
PASS IC paste 1:1 with manufacturer copper land
PASS IC paste 1:1 with manufacturer copper land
PASS IC paste 1:1 with manufacturer copper land
PASS IC paste 1:1 with manufacturer copper land
PASS self-test detects added copper inside loop
Manufacturing geometry audit passed; physical RF and supplier process acceptance remain external gates.
PASS metric 0.30 mm plated drill
PASS exactly the two antenna terminal drill positions
PASS exactly two drills
PASS only IC and terminals are exposed through mask
PASS RF keepout dimensions unchanged