pixalynx/pixal-gps

README.md

# PIXAL GPS — nRF9151 LTE-M/NB-IoT + GNSS tracker (Rev A design)

A very small rechargeable location tracker: Nordic **nRF9151** SiP (LTE-M, NB-IoT, GNSS, Cortex-M33 application MCU, no second MCU) + Nordic **nPM1300** PMIC, a removable battery cartridge with spring contacts, a Qi (BPP) wireless receiver, and an ultra-low-power accelerometer that wakes the tracker on motion. Designed for JLCPCB fabrication and assembly; firmware is expected to be developed on the nRF9151 DK first.

| Board | File | Size / layers | Contents |
| --- | --- | --- | --- |
| A — Tracker | `tracker.circuit.tsx` (also the default export of `index.circuit.tsx`) | 34 × 24 mm, 4-layer JLC04161H-7628 | nRF9151, nPM1300, LTE pi-match + U.FL, SKY65943-11 GNSS LNA/SAW + U.FL (single-antenna AUX option), nano-SIM + TPD3F303, LIS2DW12, BQ51013B Qi receiver, 4 battery spring contacts, 2×5 pogo programming/test field, button, 2 LEDs |
| B — Battery cartridge | `battery-pack.circuit.tsx` | 30 × 7 mm, 2-layer, 0.8 mm | BAT+/GND/NTC/ID gold pads, BQ29700 + FS8205A single-cell protection (or JP1 bypass for a cell with its own PCM), NTC, ID resistor |
| C — Charging dock | `dock.circuit.tsx` | 56 × 44 mm, 2-layer | USB-C 5 V → IP6829 Qi transmitter → A11 coil, 2 LEDs |

Start with [docs/design-report.md](docs/design-report.md). Everything else is in `docs/`: [rf.md](docs/rf.md) (antenna architecture and Nordic RF rules), [power.md](docs/power.md) (rails, sleep budget, battery selection), [battery-pack.md](docs/battery-pack.md) (contacts, protection policy, cartridge dimensions), [wireless-charging.md](docs/wireless-charging.md), [stackup.md](docs/stackup.md), [firmware-pinmap.md](docs/firmware-pinmap.md), [bom.md](docs/bom.md), [sources.md](docs/sources.md) (evidence map). The raw research notes with every URL are in `research/`.

## Layout of the code

- `parts/` — one typed component per IC/connector with its verified pin table and land pattern (Nordic/TI/ST/Skyworks drawings, JLC part numbers).
- `lib/footprints.tsx` — land-pattern generators (LGA-113, QFN, RHL, MCM-10, U.FL, pogo, 0806 inductor…); `lib/passives.tsx` — capacitor/resistor/inductor helpers with the JLC part-number table; `lib/geometry.ts` — board→component-local conversion for hand-routed copper; `lib/gnd-mesh.tsx` — renders the generated ground stubs.
- `routing/tracker-gnd.json` — generated by `scripts/gen-gnd-mesh.py` from the placement build: one plane via per ground land; `routing/tracker-routes.json` — the signal/power copper imported from a local Freerouting pass by `scripts/import-router-session.py`, rendered by `lib/routed-traces.tsx`. Both are geometry only; every connection is declared in `tracker.circuit.tsx`. See [docs/routing.md](docs/routing.md).
- `scripts/validate.ts` — netlist, land-coverage, routed-leg placement and DRC assertions against the built Circuit JSON; `scripts/check-clearance.py` — independent 0.10 mm copper / 0.30 mm edge audit; `scripts/audit-copper.py` — every trace joins one net; `scripts/bom.py` — BOM tables; `scripts/build.ts` — builds all three boards and runs the checks; `scripts/export-router-dsn.py`, `scripts/import-router-session.py`, `scripts/widen-power-legs.py`, `scripts/prepare-tracker-routing.sh` — the tracker routing flow.

## Run

```sh
bun install
bun run build          # all three boards → dist/<board>/{circuit.json,pcb.svg,schematic.svg}, then validate + audit
bun run build:tracker  # one board (tracker | pack | dock)
bun run check          # design assertions only (needs a previous build)
bun run dev            # tscircuit viewer on http://localhost:3900
```

Re-routing the tracker after a placement change (the build never autoroutes; `bun run check` fails until the routes match the placement):

```sh
./scripts/prepare-tracker-routing.sh && bun run route:run && bun run route:import && python3 scripts/widen-power-legs.py tracker && bun run check
```

`tmp/router/freerouting-1.9.0.jar` (Freerouting 1.9.0, Java 17) is a local development tool, not part of the design.

## Status (16 September 2026)

All three boards are fully routed, DRC-clean, and pass every design assertion (`bun run check`: 342 passed, 0 PCB errors). This is a design/prototype exercise — nothing has been fabricated, and independent review plus bench validation (see the design report's "Routing status" and "Bench gates" items) are still ahead of any order.