pixalynx/nrf9151-gps-tracker

fab/FAB-NOTES.md

# nRF9151 GPS tracker Rev A: JLCPCB order notes

Generated by `python3 scripts/export-fab.py` on 24 September 2026. The script refuses to export unless all 95 design and routing checks pass.

| File | Upload as |
| --- | --- |
| `nrf9151-gps-tracker-gerbers.zip` | PCB Gerber: 11 copper, mask, paste, silkscreen and outline layers plus 2 Excellon files (through-hole PTH with routed slots, and NPTH) |
| `nrf9151-gps-tracker-bom.csv` | Assembly BOM: 50 lines, 89 placements, LCSC part numbers (one extended part: C4, C408132) |
| `nrf9151-gps-tracker-cpl.csv` | Assembly CPL: Mid X/Y in mm, Top/Bottom, rotation in degrees counter-clockwise |

## PCB options

| Option | Setting | Why |
| --- | --- | --- |
| Layers | 4 | |
| Size | 44 × 32 mm, rounded corners | |
| Thickness | 1.6 mm | |
| Impedance control / stackup | **Yes, JLC04161H-7628** | The 50 Ω RF lines to the three U.FL connectors are sized for this stackup, referenced to the L2 ground plane |
| Copper | 1 oz outer, 0.5 oz inner | The supply-path resistance figures in docs/design.md assume this |
| Min track / space | 0.1 / 0.1 mm | |
| Min via | 0.2 mm drill / 0.4 mm pad | Below JLC's free 0.3 mm tier, so a small surcharge applies |
| Via covering | **Epoxy filled & capped** (via-in-pad) | Five lands have a via in the pad: C20.2, C22.2, R6.2 (edge ground pads), X1.1 (crystal) and C52.1 (0201). Unfilled, solder wicks away from them. The alternative is plain tented vias and accepting that risk. |
| Surface finish | **ENIG** | Flat pads for the nRF9151 LGA, the QFNs and the 0201s. HASL is too uneven for the LGA. |
| Mark on PCB (order number) | Remove, or specify a location | There is no reserved spot on this board |
| Blind / buried vias | None | All vias are through-holes (checked by the export) |

## Assembly options

- **Standard PCBA, both sides.** The top carries 55 parts, the bottom 34 (nPM1300, SIM socket and switch, LDO, crystal, the PMIC passives). Economic PCBA is single-sided only.
- **Tooling:** let JLC add the edge rails and fiducials. The board has none of its own.
- **Not placed (DNP), by design.** The pads stay empty:

  | Part | What it is | Why it's not placed |
  | --- | --- | --- |
  | U8 | MFF2 eSIM | The eUICC must come from your connectivity provider with its profile (1NCE, Onomondo, Soracom, …). Consign it to JLC or hand-solder it. The nano-SIM works without it (SIM_SEL low). |
  | J7 | Tag-Connect TC2030 SWD pads | Programming pads only; nothing to fit |
  | C10, C11 | LTE π-match shunts | Fitted only if antenna tuning asks for them. The 0 Ω series part is fitted. |
  | L3 | GNSS active-antenna bias-T | Fit it for an active GNSS antenna |

## Pick-and-place corrections

`scripts/check-jlc-footprints.py` fits every IC, connector and polarised part onto JLC's own library footprint for its LCSC number. All 28 fitted parts match; none is flagged. The CPL then carries JLC's rotation and origin instead of tscircuit's raw values:

| Part | Correction | Reason |
| --- | --- | --- |
| U9 (RT9080 LDO, bottom) | rotation 0° → **180°** | JLC flips bottom parts about the part's X axis (rotation = 180° − rot). tscircuit skips that step for a footprint with an explicit pin-1 label. |
| J1, J2, J3 (U.FL) | origin moved 0.29 mm | JLC's footprint origin is not the pad-bounding-box centre |
| J5 (USB-C) | origin moved 0.12 mm | Same reason |
| J6 (JST) | origin moved 0.10 mm | Same reason |

Fixed at the source before this export:
- **BZ1 buzzer.** The land-to-terminal mapping was rotated: + was on the mechanical tab, so the buzzer would have been silent. It now follows the Huawha datasheet drawing and JLC's library: + bottom-left, − bottom-right. It is re-routed.
- **U9 pin-1 label.** Corrected; the copper is unchanged.

## Check in JLC's SMT preview before paying

Confirm that the pin-1 dot or polarity mark sits on the marked land for each of these:
- **Top:**
  - U1 nRF9151: pin 1 at the top-left of the LGA.
  - U5 nRF7002, U2 LNA, U6 LIS2DW12.
  - D1/D2 LEDs, cathode = pad 1.
  - D3, Q1.
  - BZ1: the + land is the bottom-left one, next to the silkscreen "+".
  - Connectors: J1–J3 U.FL signal pin, J5 USB-C with its opening at the board edge, J6 JST with its opening outward, SW1 with its actuator at the edge.
- **Bottom:**
  - U3 nPM1300, U4 TPD3F303, U7 NX3DV2567, U9 RT9080.
  - J4 SIM socket, card slot at the left board edge.
  - X1 crystal (a 180° error is harmless).

If a part shows rotated in the preview, correct it there. The fitted values above come from JLC's own footprints, so a mismatch would point at a library change on their side.

## Before first power-up

- **Battery polarity.** JST pin 1 = BAT+, and there is no reverse protection. Check every cell with a meter first.
- **Charge current.** Set it to 500 mA or less in the nPM1300 configuration. VBUS is a 0.15 mm trace.
- **Bring-up order.** Follow docs/firmware.md for the nRF7002 power sequence (VBAT → BUCKEN → IOVDD) and the SIM_SEL default.
- **nRF7002 SPI pull-downs.** Configure pull-downs on P0.28/P0.29/P0.30 in the nRF9151 pinctrl (docs/firmware.md), as nRF7002 Errata [9] requires. They are not on the PCB.