pixalynx/nrf9151-gps-tracker

docs/decisions.md

# Decisions log

Decisions agreed with the owner on 2026-09-23 before layout started:

| Question | Choice | Consequence on the board |
| --- | --- | --- |
| Charging | USB-C port (power only) | nPM1300 PMIC (charger, BUCK1 1.8 V, fuel-gauge ADC, ship mode; BUCK2 disabled, see below); 6-pin TYPE-C 6P receptacle, CC1/CC2 straight to the PMIC (internal 5.1 kΩ Rd). No USB data: the nRF9151 has no USB peripheral. |
| Antennas | U.FL + stick-on flex antennas | Three Hirose U.FL-R-SMT-1 receptacles (LTE, GNSS, Wi-Fi). No antenna keep-out on the PCB; antenna choice and placement live in the enclosure. |
| Features | SOS button + 2 LEDs, motion sensor, buzzer, Wi-Fi locating | SHPHLD button, LED1/LED2 on the PMIC sinks, LIS2DW12, MLT-5020 buzzer with MOSFET driver, nRF7002 companion IC. |
| SIM / eSIM | Both fitted, switchable | Nano-SIM push-pull socket + MFF2 eSIM land pattern behind an NX3DV2567 4-pole double-throw switch (Nordic nRF9151 DK topology), SIM_SEL GPIO chooses the active card. |

Decisions taken during the design (not escalated, reversible):

- **nRF7002 instead of nRF7000.** The nRF7000 (scan-only) is not in JLCPCB's catalogue; the nRF7002 is pin-compatible, stocked (C5370744) and a functional superset. An nRF7000 can be fitted instead with no PCB change.
- **Battery connector JST-PH 2.0 mm (S2B-PH-SM4-TB), pin 1 = BAT+.** SparkFun's documented hobby-LiPo convention. About half of cell vendors reverse it, so every cell must be checked with a meter before it is plugged in. There is no reverse-polarity protection.
- **On-board 10 kΩ NTC (NCP15XH103F03RC)** on the PMIC NTC input, on the battery side of the board, so JEITA charge limits work with a 2-wire hobby cell that has no thermistor.
- **SWD on a Tag-Connect TC2030-NL footprint** (no connector fitted); logs and modem traces over SEGGER RTT, so no UART pads.
- **4-layer 1.6 mm board**, L2 an unbroken ground plane under the 50 Ω lines (same stack-up as pixal-gps).
- **RT9080 3.3 V LDO for the nRF7002 instead of BUCK2.** VSYS reaches 5.5 V on USB, and BUCK2 is limited to 200 mA against the nRF7002's 260 mA TX peak. BUCK2 is disabled (VSET2 = GND, VOUT2 tied to VSYS). The LDO is enabled from P0.02 and is off in sleep.
- **Supply path routed wide (Rev A layout, 24 Sept 2026).** VSYS/VBAT/VDD_NRF are in a 0.3 mm router class, with a 0.4 mm battery feed and a 0.25–0.35 mm VSYS feeder on the outer layers: 59 mΩ PMIC → nRF9151. VBUS stays at 0.15 mm (charge current only).
- **Via-in-pad on five lands** (C20/C22/R6 ground pads at the board edge, X1.X1, C52). These need epoxy-filled, capped vias at fabrication, a JLC option with a surcharge on 4-layer boards.
- **Renamed to "nRF9151 GPS tracker" (24 Sept 2026)** at the owner's request: project folder `nrf9151-gps-tracker`, package `@tsci/pixalynx.nrf9151-gps-tracker`, silkscreen "NRF9151 GPS TRACKER REV A".
- **Buzzer land mapping corrected (24 Sept 2026).** The MLT-5020 lands were numbered like a dfn4, which put + on the mechanical tab. They now follow the Huawha datasheet and JLC's library (+ bottom-left, − bottom-right, tab top-left), and BZ1 is re-routed. It was found by `scripts/check-jlc-footprints.py`, which the fab export now runs every time.
- **Review fixes (24 Sept 2026, after an outside review of v0.1.2).**
  - nRF7002 unused pins now follow Nordic's Revision 1 Errata [9]: pins 2–5 and 39–42 and 45 are tied to the paddle (GND); 6, 21–24, 43 and 44 stay open; the SPI_CLK/MOSI/MISO pull-downs are configured in the nRF9151 pinctrl (docs/firmware.md).
  - The nRF9151 VDD filter now follows Nordic's reference topology: C1, C2 (1 µF) and C3 (47 µF) on the VSYS side of FB1, and C4 (10 µF) between FB1 and the VDD pin. The review had proposed putting both 47 µF and 10 µF after the bead; Nordic's reference schematic puts only C4 there. C4 is a 10 V 0402 (Murata GRM155R61A106ME11D, C408132, JLC extended part), which Nordic's guidelines allow, so it fits the slot 3.6 mm from U1.VDD.
- **Second outside review (24 Sept 2026, of v0.1.3).**
  - Its proposal to move C3 (47 µF) after FB1 was not adopted. Nordic's nRF9151 PS "Reference circuitry" figure is VDD_nRF → C1, C2, C3 → FB1 → C4 → R1 → VDD. The nWP056 text "place C3 and C4 close to the VDD pin" is about placement, and C3 is 2.5 mm of 0.3 mm copper from FB1.A (4 mΩ), with FB1.B 2.5 mm from U1.VDD. The review probably read "C3 on VSYS" as "far away": Nordic's name for that net is VDD_nRF.
  - The nRF7002 block was rechecked against PS v1.3 (May 2026): same pins, values and nets. v1.3 adds an explicit power-down order, now in docs/firmware.md.