pixalynx/nrf9151-gps-tracker
A compact 44×32 mm, 4-layer nRF9151 LTE-M/NB-IoT/GNSS tracker PCB with nPM1300 LiPo/USB-C power, nano-SIM/eSIM switching, nRF7002 Wi‑Fi scanning, accelerometer, antennas, buzzer, LEDs, SOS button, and SWD/debug connectors.
- Version
- 0.1.4
- License
- unset
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- 0
dist/index.js
import { jsxs, jsx, Fragment as Fragment$1 } from 'react/jsx-runtime';
import { Fragment, Children } from 'react';
/** Land-pattern generators. Every dimension is in millimetres and is annotated
* with the manufacturer document it was read from (see docs/sources.md).
* Pin numbering follows the manufacturer's pin table; pin 1 is top-left in the
* unrotated footprint and numbering proceeds counter-clockwise for QFN/LGA
* packages (left side downwards, bottom left-to-right, right upwards, top
* right-to-left), which is the JEDEC convention used by Nordic, TI and ST. */
const pad = (pin, x, y, w, h) => (jsx(Fragment, { children: jsx("smtpad", { portHints: [typeof pin === "number" ? `pin${pin}` : pin], pcbX: x, pcbY: y, width: w, height: h, shape: "rect" }) }, `p${pin}-${x}-${y}`));
const via = (pin, x, y, drill, padD) => (jsx(Fragment, { children: jsx("platedhole", { portHints: [typeof pin === "number" ? `pin${pin}` : pin], pcbX: x, pcbY: y, holeDiameter: drill, outerDiameter: padD, shape: "circle" }) }, `v${pin}-${x}-${y}`));
const outline = (w, h, stroke = 0.12) => (jsx("silkscreenpath", { route: [{ x: -w / 2, y: -h / 2 }, { x: w / 2, y: -h / 2 }, { x: w / 2, y: h / 2 }, { x: -w / 2, y: h / 2 }, { x: -w / 2, y: -h / 2 }], strokeWidth: stroke }));
const courtyard = (w, h) => (jsx("courtyardoutline", { outline: [{ x: -w / 2, y: h / 2 }, { x: w / 2, y: h / 2 }, { x: w / 2, y: -h / 2 }, { x: -w / 2, y: -h / 2 }, { x: -w / 2, y: h / 2 }] }));
const pin1Mark = (x, y) => jsx("silkscreencircle", { pcbX: x, pcbY: y, radius: 0.15, strokeWidth: 0.1 });
/** Generic QFN/DFN land pattern.
* @param nx pins per horizontal side (top/bottom); @param ny pins per vertical side (left/right)
* @param pitch pin pitch; @param span centre-to-centre distance of opposite land rows
* @param landL land length (radial); @param landW land width (tangential)
* @param ep exposed-pad copper size (0 = none); @param epVias grid of ground vias in the EP
*/
function Qfn(p) {
const { nx, ny, pitch, spanX, landL, landW } = p;
const spanY = p.spanY ?? spanX;
const total = 2 * nx + 2 * ny;
const epPin = p.epPin ?? total + 1;
const pads = [];
let n = 1;
// left side, top to bottom
for (let i = 0; i < ny; i++)
pads.push(pad(n++, -spanX / 2, ((ny - 1) / 2 - i) * pitch, landL, landW));
// bottom, left to right
for (let i = 0; i < nx; i++)
pads.push(pad(n++, (i - (nx - 1) / 2) * pitch, -spanY / 2, landW, landL));
// right, bottom to top
for (let i = 0; i < ny; i++)
pads.push(pad(n++, spanX / 2, (i - (ny - 1) / 2) * pitch, landL, landW));
// top, right to left
for (let i = 0; i < nx; i++)
pads.push(pad(n++, ((nx - 1) / 2 - i) * pitch, spanY / 2, landW, landL));
const [epW, epH] = p.ep ? (Array.isArray(p.ep) ? p.ep : [p.ep, p.ep]) : [0, 0];
const vias = [];
if (p.epVias && epW) {
const { n: g, pitch: vp, drill, pad: vpad } = p.epVias;
for (let i = 0; i < g; i++)
for (let j = 0; j < g; j++)
vias.push(via(epPin, (i - (g - 1) / 2) * vp, (j - (g - 1) / 2) * vp, drill, vpad));
}
return (jsxs("footprint", { children: [Children.toArray(pads), epW > 0 && pad(epPin, 0, 0, epW, epH), Children.toArray(vias), outline(p.body[0], p.body[1]), pin1Mark(-p.body[0] / 2 - 0.45, p.body[1] / 2 - 0.1), courtyard(spanX + landL + 0.3, spanY + landL + 0.3)] }));
}
/** Nordic nPM1300 QFN32 5x5 mm, 0.5 mm pitch. Nordic reference layout v1.2 Gerbers
* (Altium Nordic_QFN50P500X500X90-33N): 0.30 x 0.851 mm lands, row centres +/-2.451 mm,
* exposed pad 3.5 mm (D2/E2 nominal 3.4-3.6), 9 ground vias 0.305 mm drill / 0.61 mm pad on
* a 1.2 mm grid, mask opening 3.653 mm. Pin 1 top-left, numbering counter-clockwise (JLC
* C7501206 footprint agrees on land order). */
const Npm1300Qfn32 = () => (jsx(Qfn, { nx: 8, ny: 8, pitch: 0.5, spanX: 4.902, landL: 0.85, landW: 0.30, ep: 3.5, epVias: { n: 3, pitch: 1.2, drill: 0.305, pad: 0.61 }, body: [5, 5] }));
/** Nordic nRF9151 LGA-113, 12.1 x 11.1 x 1.2 mm. 80 perimeter lands on a 0.5 mm pitch
* (20 per side; the four corner lands are 0.7 mm squares), 24 small reserved lands and
* 9 large ground lands inside. Geometry as JLC/EasyEDA C22397843 (JLCPCB assembles from
* this footprint) cross-checked against the Nordic product specification recommended
* land pattern (docs/sources.md). Pin numbering follows Nordic: pin 1 is the top-left
* corner land and numbering proceeds counter-clockwise around the perimeter (1-80), then
* the inner lands 81-113. */
function Nrf9151Lga113(p) {
const perimL = p.perimL ?? 0.45, perimW = p.perimW ?? 0.30, corner = p.cornerSq ?? 0.7, inner = p.innerSq ?? 0.2, gnd = p.gndSq ?? 1.6;
const edgeX = p.edgeX ?? 5.625, edgeY = p.edgeY ?? 5.125, cornerX = p.cornerX ?? 5.5, cornerY = p.cornerY ?? 5.0;
const pads = [];
let n = 1;
// Left column: pin 1 corner (top-left), pins 2-19 on x=-edgeX from y=+4.25 downwards, pin 20 corner (bottom-left)
pads.push(pad(n++, -cornerX, cornerY, corner, corner));
for (let i = 0; i < 18; i++)
pads.push(pad(n++, -edgeX, 4.25 - i * 0.5, perimL, perimW));
pads.push(pad(n++, -cornerX, -cornerY, corner, corner));
// Bottom row: pins 21-40 on y=-edgeY from x=-4.75 to +4.75
for (let i = 0; i < 20; i++)
pads.push(pad(n++, -4.75 + i * 0.5, -edgeY, perimW, perimL));
// Right column: pin 41 corner (bottom-right), 42-59 upwards, pin 60 corner (top-right)
pads.push(pad(n++, cornerX, -cornerY, corner, corner));
for (let i = 0; i < 18; i++)
pads.push(pad(n++, edgeX, -4.25 + i * 0.5, perimL, perimW));
pads.push(pad(n++, cornerX, cornerY, corner, corner));
// Top row: pins 61-80 on y=+edgeY from x=+4.75 to -4.75
for (let i = 0; i < 20; i++)
pads.push(pad(n++, 4.75 - i * 0.5, edgeY, perimW, perimL));
// Inner reserved lands 81-104 (0.2 mm squares): left column 81-89 (x=-4.10, y 3.40..-3.40 step 0.55/0.85 irregular
// as EasyEDA/Nordic), centre rows 90-92 (y=-2.15) and 102-104 (y=+2.15), right column 93-101.
const colY = [3.4, 2.85, 2.3, 0.55, 0, -0.55, -2.3, -2.85, -3.4];
colY.forEach((y) => pads.push(pad(n++, -4.1, y, inner, inner))) // 81-89
;
[-0.55, 0, 0.55].forEach((x) => pads.push(pad(n++, x, -2.15, inner, inner))); // 90-92
colY.slice().reverse().forEach((y) => pads.push(pad(n++, 4.1, y, inner, inner))) // 93-101 (bottom to top)
;
[0.55, 0, -0.55].forEach((x) => pads.push(pad(n++, x, 2.15, inner, inner))); // 102-104
// Ground lands 105-113 (1.6 mm squares; 108 and 112 are 1.6 x 1.95)
const gndLands = [
[-2.85, 2.85, gnd, gnd], [-2.85, 0, gnd, gnd], [-2.85, -2.85, gnd, gnd], [0, -3.575, gnd, 1.95],
[2.85, -2.85, gnd, gnd], [2.85, 0, gnd, gnd], [2.85, 2.85, gnd, gnd], [0, 3.575, gnd, 1.95], [0, 0, gnd, gnd],
];
gndLands.forEach(([x, y, w, h]) => pads.push(pad(n++, x, y, w, h)));
// Ground vias in the large ground lands (one 0.3/0.6 via each; the SiP's GND lands
// are the only path from the L1 pads to the L2 plane under the package).
const gndVias = gndLands.map(([x, y], i) => via(105 + i, x, y, 0.3, 0.6));
return (jsxs("footprint", { children: [Children.toArray(pads), Children.toArray(gndVias), outline(12.1, 11.1), pin1Mark(-6.55, 5.55), courtyard(12.5, 11.5)] }));
}
/** Hirose U.FL-R-SMT-1 (Hirose drawing, matches JLC C88374): signal land 1.0 x 1.05 mm at
* y=-1.05, two ground lands 1.05 x 2.2 mm at x=+/-1.475, y=+0.475. Cable exits along +y
* from the receptacle; the signal pad is the "1" pin. Body 2.6 x 2.6 mm. */
const UflRsmt = () => (jsxs("footprint", { insertionDirection: "from_above", children: [pad(1, 0, -1.05, 1.0, 1.05), pad(2, -1.475, 0.475, 1.05, 2.2), pad(3, 1.475, 0.475, 1.05, 2.2), outline(2.6, 2.6), courtyard(4.2, 3.3)] }));
/** ST LIS2DW12 LGA-12 2.0 x 2.0 x 0.7 mm, 0.5 mm pitch: 4 lands on the top/bottom edges
* (x = +/-0.25, +/-0.75) and 2 on each side (y = +/-0.25). Land 0.28 x 0.50 mm, centres
* 1.75 mm apart (JLC C189624; ST DS11473 Figure 12 gives the same 1.75 mm land rows). Pin 1
* is the bottom-left land in ST's top view (marked corner), numbering counter-clockwise:
* 1-4 bottom (left to right), 5-6 right (bottom to top), 7-10 top (right to left), 11-12 left
* (top to bottom). */
const Lga12_2x2 = () => (jsxs("footprint", { children: [[-0.75, -0.25, 0.25, 0.75].map((x, i) => pad(1 + i, x, -0.875, 0.28, 0.5)), pad(5, 0.875, -0.25, 0.5, 0.28), pad(6, 0.875, 0.25, 0.5, 0.28), [0.75, 0.25, -0.25, -0.75].map((x, i) => pad(7 + i, x, 0.875, 0.28, 0.5)), pad(11, -0.875, 0.25, 0.5, 0.28), pad(12, -0.875, -0.25, 0.5, 0.28), outline(2, 2), pin1Mark(-1.35, -1), courtyard(2.5, 2.5)] }));
/** 2.0 x 1.6 mm (0806 / 2016 metric) power inductor such as Murata DFE201612E / Samsung
* CIGT201610: two 0.8 x 1.6 mm lands on 1.9 mm centres (Murata DFE201612E recommended pattern
* 0.8 x 1.6, gap 1.1). */
const Ind0806 = () => (jsxs("footprint", { children: [pad(1, -0.95, 0, 0.8, 1.6), pad(2, 0.95, 0, 0.8, 1.6), outline(2.0, 1.6), courtyard(2.9, 2.0)] }));
/** Nordic nRF7002 QFN-48 6 x 6 mm, 0.4 mm pitch (nRF7002 PS v1.2 Table 26: b 0.2, L 0.4, D2/E2 4.6).
* Land geometry and pin orientation follow the JLC/EasyEDA footprint of C5370744 (tsci import matched the
* footprinter pattern qfn48 ... pin1location(bottomside,left) at 99.7 % copper IoU): 0.20 x 0.76 mm lands with
* row centres +/-2.98 mm, pin 1 at the LEFT END OF THE BOTTOM ROW and numbering counter-clockwise
* (1-12 bottom left-to-right, 13-24 right bottom-to-top, 25-36 top right-to-left, 37-48 left top-to-bottom).
* That is the datasheet top view rotated 90 degrees CCW, i.e. JLC's reel orientation. Exposed pad 49 (VSS)
* 4.6 mm with a 3 x 3 grid of 0.3/0.5 mm ground vias. */
const Nrf7002Qfn48 = () => {
const pads = [];
const r = 2.98, p = 0.4, L = 0.76, W = 0.2;
for (let i = 0; i < 12; i++)
pads.push(pad(1 + i, -2.2 + i * p, -r, W, L));
for (let i = 0; i < 12; i++)
pads.push(pad(13 + i, r, -2.2 + i * p, L, W));
for (let i = 0; i < 12; i++)
pads.push(pad(25 + i, 2.2 - i * p, r, W, L));
for (let i = 0; i < 12; i++)
pads.push(pad(37 + i, -r, 2.2 - i * p, L, W));
const vias = [];
for (const vx of [-1.4, 0, 1.4])
for (const vy of [-1.4, 0, 1.4])
vias.push(via(49, vx, vy, 0.3, 0.5));
return (jsxs("footprint", { children: [Children.toArray(pads), pad(49, 0, 0, 4.6, 4.6), Children.toArray(vias), outline(6, 6), pin1Mark(-3, -3.45), courtyard(6.8, 6.8)] }));
};
/** 2016 four-pad crystal (JLC C2835990 K2B400000810 land pattern): 0.9 x 0.8 mm lands at (+/-0.7, +/-0.55).
* Pads 1 and 3 (diagonal) are the crystal, 2 and 4 the lid/ground. */
const Crystal2016 = () => (jsxs("footprint", { children: [pad(1, -0.7, -0.55, 0.9, 0.8), pad(2, 0.7, -0.55, 0.9, 0.8), pad(3, 0.7, 0.55, 0.9, 0.8), pad(4, -0.7, 0.55, 0.9, 0.8), outline(2.0, 1.6), courtyard(2.6, 2.2)] }));
/** 0201 chip capacitor: the footprinter's 0201 lands (0.46 x 0.40 mm at +/-0.33 mm) with a courtyard drawn at the
* pad extents + 0.05 mm, so 0201 decoupling can sit at a QFN pin tip as in Nordic's nRF7002 reference layout. */
const Cap0201 = () => (jsxs("footprint", { children: [pad(1, -0.33, 0, 0.46, 0.4), pad(2, 0.33, 0, 0.46, 0.4), courtyard(1.22, 0.5)] }));
/** Nordic nRF9151 SiP (nRF9151-LACA-R7), LGA-113 12.1 x 11.1 x 1.2 mm.
* Pin table from the nRF9151 Product Specification "Pin assignments" (docs/sources.md
* [nrf9151-ps]); numbering counter-clockwise from the top-left corner (pin 1 = GND corner,
* 2-19 down the left edge, 20 corner, 21-40 bottom edge, 41 corner, 42-59 right edge,
* 60 corner, 61-80 top edge, 81-104 interior reserved, 105-113 centre GND). */
const nrf9151Pins = {
pin1: ["GND_1"], pin2: ["P0_20", "AIN7"], pin3: ["SWDCLK"], pin4: ["SWDIO"], pin5: ["P0_21", "TRACECLK"],
pin6: ["P0_22", "TRACEDATA0"], pin7: ["GND_7"], pin8: ["P0_23", "TRACEDATA1"], pin9: ["nRESET"], pin10: ["ENABLE"],
pin11: ["P0_24", "TRACEDATA2"], pin12: ["P0_25", "TRACEDATA3"], pin13: ["GND_13"], pin14: ["VDD"], pin15: ["GND_15"],
pin16: ["SIM_RST"], pin17: ["SIM_IO"], pin18: ["SIM_CLK"], pin19: ["SIM_1V8"], pin20: ["GND_20"],
pin21: ["MAGPIO0"], pin22: ["MAGPIO1"], pin23: ["MAGPIO2"], pin24: ["DEC0"], pin25: ["GND_25"], pin26: ["SIM_DET"],
pin27: ["SDATA"], pin28: ["SCLK"], pin29: ["VIO"], pin30: ["GND_30"], pin31: ["RESERVED_31"], pin32: ["RESERVED_32"],
pin33: ["RESERVED_33"], pin34: ["GND_34"], pin35: ["ANT"], pin36: ["GND_36"], pin37: ["AUX"], pin38: ["GND_38"],
pin39: ["GND_39"], pin40: ["GND_40"], pin41: ["GND_41"], pin42: ["GPS"], pin43: ["GND_43"], pin44: ["P0_26"],
pin45: ["P0_27"], pin46: ["GND_46"], pin47: ["P0_28"], pin48: ["P0_29"], pin49: ["P0_30"], pin50: ["P0_31"],
pin51: ["GND_51"], pin52: ["COEX0"], pin53: ["COEX1"], pin54: ["COEX2"], pin55: ["GND_55"], pin56: ["P0_00"],
pin57: ["P0_01"], pin58: ["P0_02"], pin59: ["P0_03"], pin60: ["GND_60"], pin61: ["P0_04"], pin62: ["P0_05"],
pin63: ["P0_06"], pin64: ["P0_07"], pin65: ["VDD_GPIO"], pin66: ["GND_66"], pin67: ["P0_08"], pin68: ["P0_09"],
pin69: ["P0_10"], pin70: ["P0_11"], pin71: ["GND_71"], pin72: ["P0_12"], pin73: ["P0_13", "AIN0"], pin74: ["P0_14", "AIN1"],
pin75: ["P0_15", "AIN2"], pin76: ["GND_76"], pin77: ["P0_16", "AIN3"], pin78: ["P0_17", "AIN4"], pin79: ["P0_18", "AIN5"],
pin80: ["P0_19", "AIN6"],
pin81: ["RESERVED_81"], pin82: ["RESERVED_82"], pin83: ["RESERVED_83"], pin84: ["RESERVED_84"], pin85: ["RESERVED_85"],
pin86: ["RESERVED_86"], pin87: ["RESERVED_87"], pin88: ["RESERVED_88"], pin89: ["RESERVED_89"], pin90: ["RESERVED_90"],
pin91: ["RESERVED_91"], pin92: ["RESERVED_92"], pin93: ["RESERVED_93"], pin94: ["RESERVED_94"], pin95: ["RESERVED_95"],
pin96: ["RESERVED_96"], pin97: ["RESERVED_97"], pin98: ["RESERVED_98"], pin99: ["RESERVED_99"], pin100: ["RESERVED_100"],
pin101: ["RESERVED_101"], pin102: ["RESERVED_102"], pin103: ["RESERVED_103"], pin104: ["RESERVED_104"],
pin105: ["GND_105"], pin106: ["GND_106"], pin107: ["GND_107"], pin108: ["GND_108"], pin109: ["GND_109"],
pin110: ["GND_110"], pin111: ["GND_111"], pin112: ["GND_112"], pin113: ["GND_113"],
};
/** All ground lands. Pins 15 and 40 reach ground only through the SiP's conformal shield and
* are not a signal reference (Nordic HDG "GND"); they are still tied to GND here. */
const nrf9151GndPins = ["GND_1", "GND_7", "GND_13", "GND_15", "GND_20", "GND_25", "GND_30", "GND_34", "GND_36", "GND_38", "GND_39", "GND_40", "GND_41", "GND_43", "GND_46", "GND_51", "GND_55", "GND_60", "GND_66", "GND_71", "GND_76", "GND_105", "GND_106", "GND_107", "GND_108", "GND_109", "GND_110", "GND_111", "GND_112", "GND_113"];
const Nrf9151 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "nRF9151-LACA-R7", supplierPartNumbers: { jlcpcb: ["C22397843"] }, pinLabels: nrf9151Pins, internallyConnectedPins: [[...nrf9151GndPins]], footprint: jsx(Nrf9151Lga113, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C22397843.obj?uuid=c99b497c192940919af8e3c7060d37d3", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schWidth: 1.4, schHeight: 5.9, schPinArrangement: {
// two balanced columns (30 / 29): tsci's schematic-placement rules only accept pin padding of one pitch on a
// side with several pins, which rules out uneven columns or a short GND row under a wide box
leftSide: { direction: "top-to-bottom", pins: ["VDD", "VDD_GPIO", "VIO", "GND_1", "GND_112", "GND_113", "ENABLE", "nRESET", "DEC0", "SWDCLK", "SWDIO", "SIM_1V8", "SIM_RST", "SIM_CLK", "SIM_IO", "SIM_DET", "COEX0", "COEX1", "COEX2", "MAGPIO0", "MAGPIO1", "MAGPIO2", "SCLK", "SDATA", "P0_26", "P0_27", "P0_28", "P0_29", "P0_30", "P0_31"] },
rightSide: { direction: "top-to-bottom", pins: ["ANT", "AUX", "GPS", "P0_00", "P0_01", "P0_02", "P0_03", "P0_04", "P0_05", "P0_06", "P0_07", "P0_08", "P0_09", "P0_10", "P0_11", "P0_12", "P0_13", "P0_14", "P0_15", "P0_16", "P0_17", "P0_18", "P0_19", "P0_20", "P0_21", "P0_22", "P0_23", "P0_24", "P0_25"] },
}, pinAttributes: {
VDD: { requiresPower: true }, VDD_GPIO: { requiresPower: true }, ENABLE: { mustBeConnected: true }, DEC0: { mustBeConnected: true },
SIM_1V8: { providesPower: true }, VIO: { providesPower: true }, SIM_DET: { doNotConnect: true },
GND_1: { requiresGround: true }, GND_112: { requiresGround: true }, GND_113: { requiresGround: true },
...Object.fromEntries(Array.from({ length: 24 }, (_, i) => [`RESERVED_${81 + i}`, { doNotConnect: true }])),
RESERVED_31: { doNotConnect: true }, RESERVED_32: { doNotConnect: true }, RESERVED_33: { doNotConnect: true },
} }));
/** Nordic nPM1300 PMIC, QFN32 5x5 mm (nPM1300-QEAA-R7). Pin table from the nPM1300
* Product Specification v1.3 "Pin assignments" (docs/sources.md [npm1300-ps]). */
const npm1300Pins = {
pin1: ["VOUT1"], pin2: ["PVSS1"], pin3: ["SW1"], pin4: ["PVDD"], pin5: ["SW2"], pin6: ["PVSS2"],
pin7: ["GPIO0"], pin8: ["GPIO1"], pin9: ["GPIO2"], pin10: ["GPIO3"], pin11: ["GPIO4"], pin12: ["VDDIO"],
pin13: ["SDA"], pin14: ["SCL"], pin15: ["SHPHLD"], pin16: ["VSET2"], pin17: ["VSET1"], pin18: ["NTC"],
pin19: ["VBAT"], pin20: ["VSYS"], pin21: ["VBUS"], pin22: ["VBUSOUT"], pin23: ["CC1"], pin24: ["CC2"],
pin25: ["LED0"], pin26: ["LED1"], pin27: ["LED2"], pin28: ["LSIN1", "VINLDO1"], pin29: ["LSOUT1", "VOUTLDO1"],
pin30: ["LSIN2", "VINLDO2"], pin31: ["LSOUT2", "VOUTLDO2"], pin32: ["VOUT2"], pin33: ["AVSS", "GND"],
};
const Npm1300 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "nPM1300-QEAA-R7", supplierPartNumbers: { jlcpcb: ["C7501206"] }, pinLabels: npm1300Pins, internallyConnectedPins: [["AVSS", "PVSS1", "PVSS2"]], footprint: jsx(Npm1300Qfn32, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C7501206.obj?uuid=595304ab79a843bfa03bdaf869386976", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schWidth: 1.55, schHeight: 3.55, schPinArrangement: {
leftSide: { direction: "top-to-bottom", pins: ["VBUS", "VBUSOUT", "CC1", "CC2", "VBAT", "NTC", "SHPHLD", "VSET1", "VSET2", "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4"] },
rightSide: { direction: "top-to-bottom", pins: ["VSYS", "PVDD", "SW1", "VOUT1", "PVSS1", "SW2", "VOUT2", "PVSS2", "LSIN1", "LSOUT1", "LSIN2", "LSOUT2", "LED0", "LED1", "LED2"] },
topSide: { direction: "left-to-right", pins: ["VDDIO", "SDA", "SCL"] },
bottomSide: { direction: "left-to-right", pins: ["AVSS"] },
}, pinAttributes: {
VBUS: { requiresPower: true }, VBAT: { requiresPower: true }, PVDD: { requiresPower: true },
VSYS: { providesPower: true }, VOUT1: { providesPower: true }, VOUT2: { providesPower: true }, VDDIO: { requiresPower: true },
AVSS: { requiresGround: true }, PVSS1: { requiresGround: true }, PVSS2: { requiresGround: true },
VSET1: { mustBeConnected: true }, VSET2: { mustBeConnected: true }, NTC: { mustBeConnected: true }, VBUSOUT: { mustBeConnected: true },
} }));
/** ST LIS2DW12 3-axis accelerometer, LGA-12 2x2x0.7 mm. Pin table from ST DS11473
* (docs/sources.md [lis2dw12]): 1 SCL/SPC, 2 CS, 3 SDO/SA0, 4 SDA/SDI/SDO, 5 NC, 6 GND,
* 7 RES (connect to GND), 8 GND, 9 VDD, 10 VDD_IO, 11 INT2, 12 INT1. */
const lis2dw12Pins = {
pin1: ["SCL", "SPC"], pin2: ["CS"], pin3: ["SDO", "SA0"], pin4: ["SDA", "SDI"], pin5: ["NC"], pin6: ["GND1"],
pin7: ["RES"], pin8: ["GND2"], pin9: ["VDD"], pin10: ["VDD_IO"], pin11: ["INT2"], pin12: ["INT1"],
};
const Lis2dw12 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "LIS2DW12TR", supplierPartNumbers: { jlcpcb: ["C189624"] }, pinLabels: lis2dw12Pins, internallyConnectedPins: [["GND1", "GND2"]], footprint: jsx(Lga12_2x2, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C189624.obj?uuid=83ec6157b4954879af30009d604f164f", rotationOffset: { x: 0, y: 0, z: 90 }, positionOffset: { x: 0, y: 0, z: 0 } }, schPinArrangement: {
leftSide: { direction: "top-to-bottom", pins: ["VDD", "VDD_IO", "SCL", "SDA", "SA0", "CS"] },
rightSide: { direction: "top-to-bottom", pins: ["INT1", "INT2", "NC", "GND1", "GND2", "RES"] },
}, pinAttributes: { VDD: { requiresPower: true }, VDD_IO: { requiresPower: true }, GND1: { requiresGround: true }, GND2: { requiresGround: true }, RES: { requiresGround: true }, CS: { mustBeConnected: true }, SA0: { mustBeConnected: true }, NC: { doNotConnect: true } } }));
/** Nano-SIM (4FF) socket SMN-304 (push-pull, no card-detect switch; SIM_DET is unused on the nRF9151 anyway)
* NOTE: no courtyard is declared on purpose: the socket body sits over the nRF9151 ground vias on the
* other side of the board, and the placement checker flags any through-hole under a courtyard.
* Bottom-side neighbours are kept clear of the socket by the placement audit in scripts/validate.ts.
* Original description: SMN-304 (JLC C266889): six ISO 7816 contacts plus two shell/
* mounting lands and two locating pegs. Land pattern is the JLC/EasyEDA footprint that JLCPCB
* assembles from (see docs/sources.md). Contact naming follows ISO 7816-2: C1 VCC, C2 RST,
* C3 CLK, C5 GND, C6 VPP (unused), C7 I/O. Pins 1 and 2 are the metal shell lands (GND). */
const pinLabels = {
pin1: ["SHELL1"],
pin2: ["SHELL2"],
pin3: ["C7", "IO"],
pin4: ["C6", "VPP"],
pin5: ["C5", "GND"],
pin6: ["C3", "CLK"],
pin7: ["C2", "RST"],
pin8: ["C1", "VCC"]
};
const NanoSimSocket = (props) => {
return (jsx("chip", { pinLabels: pinLabels, internallyConnectedPins: [["SHELL1", "SHELL2"]], schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["VCC", "RST", "CLK", "IO", "VPP", "GND", "SHELL1", "SHELL2"] } }, pinAttributes: { GND: { requiresGround: true }, SHELL1: { requiresGround: true }, VPP: { doNotConnect: true } }, supplierPartNumbers: {
"jlcpcb": [
"C266889"
]
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objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C266889.obj?uuid=e188f44e57f64fb0a0cea1dace9b73a2",
stepUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C266889.step?uuid=e188f44e57f64fb0a0cea1dace9b73a2",
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};
/** Skyworks SKY65943-11 GNSS LNA front-end module with integrated pre- and post-filters,
* 10-pin MCM 2.5 x 2.5 mm (JLC C2654442). Pin table from the Skyworks datasheet 204404H
* (docs/sources.md [sky65943]): 1 GND, 2 VEN, 3 VCC, 4 GND, 5 RF_IN, 6 GND, 7 FILT_OUT,
* 8 AMP_IN, 9 GND, 10 RF_OUT, plus the ground paddle. Supply 1.62-3.3 V, 2.9 mA at 1.8 V,
* 0.1 uA when VEN is low. The land pattern is the JLC/EasyEDA one: 0.30 x 0.50 mm lands on
* a 0.5 mm pitch in two rows 2.4 mm apart, 0.52 mm-wide corner lands, 2.1 x 1.4 mm paddle. */
const Mcm10 = () => (jsxs("footprint", { children: [pad(1, -1.144, -1.2, 0.52, 0.5), pad(2, -0.5, -1.2, 0.3, 0.5), pad(3, 0, -1.2, 0.3, 0.5), pad(4, 0.5, -1.2, 0.3, 0.5), pad(5, 1.144, -1.2, 0.52, 0.5), pad(6, 1.144, 1.2, 0.52, 0.5), pad(7, 0.5, 1.2, 0.3, 0.5), pad(8, 0, 1.2, 0.3, 0.5), pad(9, -0.5, 1.2, 0.3, 0.5), pad(10, -1.144, 1.2, 0.52, 0.5), pad(11, 0, 0, 2.1, 1.4), via(11, -0.55, 0, 0.25, 0.5), via(11, 0.55, 0, 0.25, 0.5), outline(2.5, 2.5), jsx("silkscreencircle", { pcbX: -1.75, pcbY: -1.6, radius: 0.15, strokeWidth: 0.1 }), courtyard(2.9, 2.9)] }));
const sky65943Pins = {
pin1: ["GND1"], pin2: ["VEN"], pin3: ["VCC"], pin4: ["GND2"], pin5: ["RF_IN"], pin6: ["GND3"], pin7: ["FILT_OUT"],
pin8: ["AMP_IN"], pin9: ["GND4"], pin10: ["RF_OUT"], pin11: ["GND_PAD"],
};
const Sky65943 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "SKY65943-11", supplierPartNumbers: { jlcpcb: ["C2654442"] }, pinLabels: sky65943Pins, internallyConnectedPins: [["GND1", "GND2", "GND3", "GND4", "GND_PAD"]], footprint: jsx(Mcm10, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C2654442.obj?uuid=77bfbb36aeda4085ae11f0a14d6642aa", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schPinArrangement: {
leftSide: { direction: "top-to-bottom", pins: ["RF_IN", "VEN", "VCC", "GND1"] },
rightSide: { direction: "top-to-bottom", pins: ["RF_OUT", "FILT_OUT", "AMP_IN", "GND_PAD"] },
}, pinAttributes: { VCC: { requiresPower: true }, GND1: { requiresGround: true }, GND_PAD: { requiresGround: true }, VEN: { mustBeConnected: true }, FILT_OUT: { mustBeConnected: true }, AMP_IN: { mustBeConnected: true } } }));
/** TI TPD3F303 SIM-card EMI filter + ESD array, USON-8 with ground paddle 1.6 x 2.1 mm (DPV;
* JLC C2865991). Pin table from TI SLLSEM8 (docs/sources.md [tpd3f303]): 1 DATA1_OUT,
* 2 CLK_OUT, 3 DATA2_OUT, 4 NC, 5 VCC (ESD clamp only, the supply is not routed through the
* device), 6 DATA2_IN, 7 CLK_IN, 8 DATA1_IN; paddle = GND, "connect ... to the printed circuit
* board ground plane through vias directly under the package". The pi filters are 45 ohm (CLK)
* and 100 ohm (DATA) series with ~20 pF shunt capacitance; OUT pins face the SIM socket. */
const Uson8Ep = () => (jsxs("footprint", { children: [[1, 2, 3, 4].map((p, i) => pad(p, -0.75 + i * 0.5, -0.722, 0.28, 0.553)), [5, 6, 7, 8].map((p, i) => pad(p, 0.75 - i * 0.5, 0.722, 0.28, 0.553)), pad(9, 0, 0, 1.7, 0.4), outline(2.1, 1.6), jsx("silkscreencircle", { pcbX: -1.35, pcbY: -1.1, radius: 0.15, strokeWidth: 0.1 }), courtyard(2.4, 2.1)] }));
const tpd3f303Pins = {
pin1: ["DATA1_OUT"], pin2: ["CLK_OUT"], pin3: ["DATA2_OUT"], pin4: ["NC"], pin5: ["VCC"], pin6: ["DATA2_IN"], pin7: ["CLK_IN"], pin8: ["DATA1_IN"], pin9: ["GND"],
};
const Tpd3f303 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "TPD3F303DPVR", supplierPartNumbers: { jlcpcb: ["C2865991"] }, pinLabels: tpd3f303Pins, footprint: jsx(Uson8Ep, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C2865991.obj?uuid=8931da5bc9704afdbe04de1fc09f054d", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schWidth: 2.1, schHeight: 0.7, schPinArrangement: {
leftSide: { direction: "top-to-bottom", pins: ["DATA1_IN", "CLK_IN", "DATA2_IN", "VCC"] },
rightSide: { direction: "top-to-bottom", pins: ["DATA1_OUT", "CLK_OUT", "DATA2_OUT", "NC"] },
bottomSide: { direction: "left-to-right", pins: ["GND"] },
}, pinAttributes: { GND: { requiresGround: true }, VCC: { requiresPower: true }, NC: { doNotConnect: true } } }));
/** Panasonic EVQP7A01P side-actuated tactile switch, 3.5 x 3.6 x 1.35 mm (JLC C79167).
* Four lands; pins 1/1' are one contact, 2/2' the other (EasyEDA pin 3 = 1', pin 4 = 2'). */
const EvqP7 = () => (jsxs("footprint", { insertionDirection: "from_right", cutoutApertureDirection: "from_right", children: [pad(1, -1.8, 0.725, 1.4, 1.05), pad(2, -1.8, -0.725, 1.4, 1.05), pad(3, 1.8, 0.725, 1.4, 1.05), pad(4, 1.8, -0.725, 1.4, 1.05), outline(3.5, 3.6), courtyard(5.0, 3.8)] }));
const tactPins = { pin1: ["A"], pin2: ["B"], pin3: ["A2"], pin4: ["B2"] };
const TactSwitch = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "EVQP7A01P", supplierPartNumbers: { jlcpcb: ["C79167"] }, pinLabels: tactPins, internallyConnectedPins: [["A", "A2"], ["B", "B2"]], footprint: jsx(EvqP7, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C79167.obj?uuid=86f037ec24a240509f30a5629d3af720", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["A"] }, rightSide: { direction: "top-to-bottom", pins: ["B"] } } }));
/** Hirose U.FL-R-SMT-1(80) receptacle (JLC C88374, 393k in stock). Pin 1 = centre
* conductor, pins 2/3 = shield/ground. */
const uflPins = { pin1: ["SIG"], pin2: ["GND1"], pin3: ["GND2"] };
const Ufl = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "U.FL-R-SMT-1(80)", supplierPartNumbers: { jlcpcb: ["C88374"] }, pinLabels: uflPins, internallyConnectedPins: [["GND1", "GND2"]], footprint: jsx(UflRsmt, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C88374.obj?uuid=286ce1aee5764889ae249e36cfa94f79", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schWidth: 0.45, schHeight: 1.15, schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["SIG"] }, bottomSide: { direction: "left-to-right", pins: ["GND1", "GND2"] } }, pinAttributes: { GND1: { requiresGround: true }, GND2: { requiresGround: true } } }));
/** Tag-Connect TC2030-IDC-NL / TC2030-CTX-NL "plug-of-nails" SWD footprint: no component is fitted,
* the cable's spring pins press on six bare pads. Geometry from KiCad's
* Tag-Connect_TC2030-IDC-NL_2x03_P1.27mm_Vertical (converted to y-up): 0.787 mm pads on a 1.27 mm grid,
* odd pins on the lower row with pin 1 next to the single 0.99 mm locating hole, two more holes at the
* other end. Signals per Tag-Connect TC2030-CTX: 1 VCC (target reference), 2 SWDIO, 3 nRESET,
* 4 SWCLK, 5 GND, 6 SWO. The nRF9151 has no SWO pin, so pad 6 stays unconnected; logs and modem
* traces go over SEGGER RTT on the same SWD link. */
const tc2030Pins = { pin1: ["VREF"], pin2: ["SWDIO"], pin3: ["NRESET"], pin4: ["SWCLK"], pin5: ["GND"], pin6: ["SWO"] };
const Tc2030 = (props) => (jsx("chip", { ...props, pinLabels: tc2030Pins, doNotPlace: true, footprint: jsxs("footprint", { insertionDirection: "from_above", children: [[1, 3, 5].map((p, i) => jsx("smtpad", { portHints: [`pin${p}`], pcbX: -1.27 + i * 1.27, pcbY: -0.635, radius: 0.3937, shape: "circle" }, p)), [2, 4, 6].map((p, i) => jsx("smtpad", { portHints: [`pin${p}`], pcbX: -1.27 + i * 1.27, pcbY: 0.635, radius: 0.3937, shape: "circle" }, p)), jsx("hole", { pcbX: -2.54, pcbY: 0, diameter: 0.9906 }), jsx("hole", { pcbX: 2.54, pcbY: -1.016, diameter: 0.9906 }), jsx("hole", { pcbX: 2.54, pcbY: 1.016, diameter: 0.9906 }), jsx("silkscreentext", { text: "SWD", pcbX: 0, pcbY: 1.75, fontSize: 0.6, anchorAlignment: "center" })] }), schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["VREF", "SWDIO", "NRESET", "SWCLK", "SWO", "GND"] } }, pinAttributes: { GND: { requiresGround: true }, SWO: { doNotConnect: true } } }));
/** USB-C 6-pin power-only receptacle "TYPE-C 6P" (JLC C456012, 527k in stock): GND, VBUS, CC1,
* CC2, VBUS, GND plus four plated shell legs. Charging only: the nRF9151 has no USB peripheral,
* so there are no D+/D- contacts. The nPM1300 CC1/CC2 pins carry the 5.1 kOhm Rd pull-downs
* internally (nPM1300 PS SYSREG), so the CC lines go straight to the PMIC.
* Geometry: the EasyEDA footprint of C456012 (tsci import), contact row at +y, the plug enters
* from -y. Core centres the footprint on its pad bounds, so relative to pcbX/pcbY the contacts sit
* at y = +2.15, the shell legs at +/-1.9 and the receptacle mouth (body front) at y = -3.5. */
const usbC6pPins = {
pin1: ["GND1"], pin2: ["VBUS1"], pin3: ["CC1"], pin4: ["CC2"], pin5: ["VBUS2"], pin6: ["GND2"],
pin7: ["SHELL1"], pin8: ["SHELL2"], pin9: ["SHELL3"], pin10: ["SHELL4"],
};
const UsbC6p = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "TYPE-C 6P", supplierPartNumbers: { jlcpcb: ["C456012"] }, pinLabels: usbC6pPins, internallyConnectedPins: [["GND1", "GND2", "SHELL1", "SHELL2", "SHELL3", "SHELL4"], ["VBUS1", "VBUS2"]], footprint: jsxs("footprint", { insertionDirection: "from_y_neg", children: [pad(1, -2.7, 1.75, 0.8, 1.2), pad(2, -1.5, 1.75, 0.7, 1.2), pad(3, -0.5, 1.75, 0.7, 1.2), pad(4, 0.5, 1.75, 0.7, 1.2), pad(5, 1.5, 1.75, 0.7, 1.2), pad(6, 2.7, 1.75, 0.8, 1.2), [[-4.32, 1.5], [4.32, 1.5], [-4.32, -2.3], [4.32, -2.3]].map(([x, y], i) => (jsx("platedhole", { portHints: [`pin${7 + i}`], pcbX: x, pcbY: y, shape: "pill", holeWidth: 0.6, holeHeight: 1.4, outerWidth: 1.1, outerHeight: 1.9 }, `sh${i}`))), jsx("silkscreenpath", { route: [{ x: -4.47, y: -3.9 }, { x: 4.47, y: -3.9 }], strokeWidth: 0.12 }), jsx("courtyardoutline", { outline: [{ x: -5.1, y: 2.7 }, { x: 5.1, y: 2.7 }, { x: 5.1, y: -4 }, { x: -5.1, y: -4 }, { x: -5.1, y: 2.7 }] })] }), cadModel: {
objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C456012.obj?uuid=a8c86ef7d632469a8c796c24a9574b1e",
stepUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C456012.step?uuid=a8c86ef7d632469a8c796c24a9574b1e",
pcbRotationOffset: 180,
modelOriginPosition: { x: 0, y: -2.2999, z: 0.06 },
}, schPinArrangement: { rightSide: { direction: "top-to-bottom", pins: ["VBUS1", "VBUS2", "CC1", "CC2", "GND1", "GND2", "SHELL1", "SHELL2", "SHELL3", "SHELL4"] } }, pinAttributes: { GND1: { requiresGround: true }, GND2: { requiresGround: true }, SHELL1: { requiresGround: true }, VBUS1: { providesPower: true } } }));
/** JST PH 2.0 mm 2-pin SMD right-angle header S2B-PH-SM4-TB(LF)(SN) (JLC C295747, 113k in stock).
* Footprint from the tsci import of C295747 (100 % copper match to footprinter "fpc2"). Relative to the
* component centre (pad-bounds centre): contacts 1.0 x 3.8 mm at (-1, +2.82) pin 1 and (+1, +2.82) pin 2,
* retention lands 1.5 x 3.4 mm at (+/-3.35, -3.02). Wire entry is on the retention-land side (-y
* unrotated; JST ePH drawing), so rotate 180 degrees for a +y opening.
* Pin 1 = BAT+ (red) and pin 2 = BAT- (black) is SparkFun's documented JST-PH LiPo convention
* (learn.sparkfun.com "Single Cell LiPo Battery Care", JST-PH connectors). About half of the cell
* vendors wire it the other way: check every purchased cell with a meter before plugging it in. */
const jstPh2Pins = { pin1: ["BAT_P"], pin2: ["BAT_N"], pin3: ["MNT1"], pin4: ["MNT2"] };
const JstPh2 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "S2B-PH-SM4-TB(LF)(SN)", supplierPartNumbers: { jlcpcb: ["C295747"] }, pinLabels: jstPh2Pins, footprint: jsxs("footprint", { insertionDirection: "from_y_neg", children: [jsx("smtpad", { portHints: ["pin1"], pcbX: -1, pcbY: 0, width: 1, height: 3.8, shape: "rect" }), jsx("smtpad", { portHints: ["pin2"], pcbX: 1, pcbY: 0, width: 1, height: 3.8, shape: "rect" }), jsx("smtpad", { portHints: ["pin3"], pcbX: 3.35, pcbY: -5.85, width: 1.5, height: 3.4, shape: "rect" }), jsx("smtpad", { portHints: ["pin4"], pcbX: -3.35, pcbY: -5.85, width: 1.5, height: 3.4, shape: "rect" }), jsx("silkscreenpath", { route: [{ x: -3.9, y: 1.1 }, { x: -3.9, y: -3.6 }], strokeWidth: 0.12 }), jsx("silkscreenpath", { route: [{ x: 3.9, y: 1.1 }, { x: 3.9, y: -3.6 }], strokeWidth: 0.12 }), jsx("silkscreentext", { text: "+", pcbX: -1, pcbY: 2.5, fontSize: 0.8, anchorAlignment: "center" }), jsx("courtyardoutline", { outline: [{ x: -4.35, y: 2.2 }, { x: 4.35, y: 2.2 }, { x: 4.35, y: -7.8 }, { x: -4.35, y: -7.8 }, { x: -4.35, y: 2.2 }] })] }), cadModel: {
objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C295747.obj?uuid=e009435048914ef2b30a218c3065ed28",
stepUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C295747.step?uuid=e009435048914ef2b30a218c3065ed28",
pcbRotationOffset: 0,
modelOriginPosition: { x: -1, y: 2.85, z: 0 },
}, schPinArrangement: { rightSide: { direction: "top-to-bottom", pins: ["BAT_P", "BAT_N", "MNT1", "MNT2"] } }, pinAttributes: { BAT_N: { requiresGround: true }, BAT_P: { providesPower: true } } }));
/** Jiangsu Huawha MLT-5020 5.0 x 5.0 x 2.0 mm SMD electromagnetic buzzer (JLC C94598, 106k in stock):
* 2-4 V (3 V rated), 100 mA max, resonant 4 kHz, 75 dB at 10 cm. Magnetic transducer = coil, so it
* needs a square-wave drive near 4 kHz (nRF9151 PWM) through a low-side MOSFET and a flyback diode.
* Land pattern and numbering = the JLC/EasyEDA library footprint, which matches the Huawha datasheet dimension
* drawing (top view): pad 1 "+" bottom-left, pad 2 "-" bottom-right, pad 3 mechanical tab (NC) top-left, the
* top-right corner is the body's chamfer and has no land. 1.7 x 0.7 mm lands on a 4.6 x 3.5 mm grid. Numbering
* matches JLC's so the pick-and-place rotation check works. (Until 2026-09-24 the lands were numbered like a dfn4,
* which put "+" on the mechanical tab: the buzzer would have been silent.) */
const buzzerPins = { pin1: ["POS"], pin2: ["NEG"], pin3: ["NC"] };
const Buzzer = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "MLT-5020", supplierPartNumbers: { jlcpcb: ["C94598"] }, pinLabels: buzzerPins, footprint: jsxs("footprint", { children: [pad(1, -2.3, -1.75, 1.7, 0.7), pad(2, 2.3, -1.75, 1.7, 0.7), pad(3, -2.3, 1.75, 1.7, 0.7), jsx("silkscreenpath", { route: [{ x: -2.5, y: 2.5 }, { x: 2.5, y: 2.5 }], strokeWidth: 0.12 }), jsx("silkscreenpath", { route: [{ x: -2.5, y: -2.5 }, { x: 2.5, y: -2.5 }], strokeWidth: 0.12 }), jsx("silkscreenpath", { route: [{ x: -2.5, y: -1.2 }, { x: -2.5, y: 1.2 }], strokeWidth: 0.12 }), jsx("silkscreenpath", { route: [{ x: 2.5, y: -1.2 }, { x: 2.5, y: 1.2 }], strokeWidth: 0.12 }), jsx("silkscreentext", { text: "+", pcbX: -0.8, pcbY: -1.75, fontSize: 0.8 }), courtyard(6.8, 5.1)] }), cadModel: {
objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C94598.obj?uuid=5e71db11d9fa48278b90d6344e196479",
stepUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C94598.step?uuid=5e71db11d9fa48278b90d6344e196479",
pcbRotationOffset: 270,
modelOriginPosition: { x: 0, y: 0.06, z: 0 },
}, schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["POS", "NEG"] }, rightSide: { direction: "top-to-bottom", pins: ["NC"] } }, pinAttributes: { NC: { doNotConnect: true } } }));
/** Diodes Inc DMG1012T-7 N-MOSFET, SOT-523 (JLC C20512): 20 V, 630 mA, RDS(on) 500 mOhm at
* VGS = 1.8 V, so the 1.8 V nRF9151 GPIO switches it fully. Pins 1 G, 2 S, 3 D. Footprint = the
* EasyEDA land pattern of C20512 (0.51 x 0.40 mm lands). */
const nmosPins = { pin1: ["G"], pin2: ["S"], pin3: ["D"] };
const Dmg1012t = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "DMG1012T-7", supplierPartNumbers: { jlcpcb: ["C20512"] }, pinLabels: nmosPins, footprint: jsxs("footprint", { children: [pad(3, -0.65, 0, 0.51, 0.4), pad(1, 0.65, -0.5, 0.51, 0.4), pad(2, 0.65, 0.5, 0.51, 0.4), outline(0.8, 1.6), courtyard(2.1, 2.0)] }), cadModel: {
objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C20512.obj?uuid=3dc99d09648d4392979bbf6561129f61",
stepUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C20512.step?uuid=3dc99d09648d4392979bbf6561129f61",
pcbRotationOffset: 180,
modelOriginPosition: { x: 0, y: 0, z: -0.149 },
}, schWidth: 1.2, schHeight: 1.2, schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["G"] }, topSide: { direction: "left-to-right", pins: ["D"] }, bottomSide: { direction: "left-to-right", pins: ["S"] } } }));
/** onsemi RB521S30T1G 30 V / 200 mA Schottky, SOD-523 (JLC C145179): buzzer flyback clamp.
* EasyEDA land pattern: two 0.6 x 0.36 mm lands, 1.3 mm apart; pin 1 = cathode. */
const schottkyPins = { pin1: ["K", "cathode"], pin2: ["A", "anode"] };
const Rb521s30 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "RB521S30T1G", supplierPartNumbers: { jlcpcb: ["C145179"] }, pinLabels: schottkyPins, footprint: jsxs("footprint", { children: [pad(1, -0.65, 0, 0.6, 0.36), pad(2, 0.65, 0, 0.6, 0.36), jsx("silkscreenpath", { route: [{ x: -1.1, y: -0.35 }, { x: -1.1, y: 0.35 }], strokeWidth: 0.1 }), courtyard(2.2, 1.0)] }), cadModel: {
objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C145179.obj?uuid=1b4f85e18594402ead7ab158b0198846",
stepUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C145179.step?uuid=1b4f85e18594402ead7ab158b0198846",
pcbRotationOffset: 180,
modelOriginPosition: { x: -0.213, y: -0.011, z: -0.71 },
}, schWidth: 0.6, schHeight: 1, schPinArrangement: { topSide: { direction: "left-to-right", pins: ["K"] }, bottomSide: { direction: "left-to-right", pins: ["A"] } } }));
/** Nordic nRF7002-QFAA-R7 Wi-Fi 6 companion IC (JLC C5370744), used here only for SSID scanning (Wi-Fi
* positioning). The nRF7000 (scan-only variant) is pin compatible. Pin table: nRF7002 Product
* Specification v1.2 Table 24, rechecked against v1.3 (May 2026) Table 1 (research/nrf7002.md), with the unused-pin handling of nRF7002 Revision 1 Errata
* [9] ("IOVDD leakage current increases with floating pins"): pins 2-5 (renamed Reserved) and the unused
* 39 QSPI_DATA2, 40 QSPI_DATA3, 41 COEX_STATUS0, 42 COEX_REQ, 45 COEX_STATUS1/SW_CTRL1 go to GND; 6, 21-24,
* 43, 44 stay open; 35/37/38 (SPI CLK/MOSI/MISO) need pull-downs, done in the host GPIO configuration
* (docs/firmware.md), which the erratum allows. VBAT 2.9-4.5 V, IOVDD 1.62-3.6 V, shutdown 1.7 uA,
* scan 60 mA average, TX 191 mA (2.4 GHz) / 260 mA (5 GHz) peak. */
const nrf7002Pins = {
pin1: ["OTPVDD"], pin2: ["RSV2"], pin3: ["RSV3"], pin4: ["RSV4"], pin5: ["RSV5"], pin6: ["RSV6"],
pin7: ["TXRF1"], pin8: ["PAVDD1"], pin9: ["TXRF0"], pin10: ["PAVDD0"], pin11: ["SXLDO"], pin12: ["PALDO"],
pin13: ["VBAT"], pin14: ["RFVDD"], pin15: ["RFBUCKVDD"], pin16: ["XOLDO"], pin17: ["XOP"], pin18: ["XON"],
pin19: ["AFELDO"], pin20: ["AFEVBAT"], pin21: ["NC21"], pin22: ["NC22"], pin23: ["NC23"], pin24: ["NC24"],
pin25: ["BUCKVBAT"], pin26: ["BUCKOUT"], pin27: ["BUCKVSS1"], pin28: ["BUCKVSS2"], pin29: ["BUCKVMID"], pin30: ["BUCKEN"],
pin31: ["BUCKVBATS"], pin32: ["PWRBUCKVDD"], pin33: ["DIGVDD"], pin34: ["PWRIOVDD"],
pin35: ["SPI_CLK", "QSPI_CLK"], pin36: ["SPI_SS", "QSPI_SS"], pin37: ["SPI_MOSI", "QSPI_DATA0"], pin38: ["SPI_MISO", "QSPI_DATA1"],
pin39: ["QSPI_DATA2"], pin40: ["QSPI_DATA3"], pin41: ["COEX_STATUS0"], pin42: ["COEX_REQ"], pin43: ["COEX_GRANT"],
pin44: ["SW_CTRL0"], pin45: ["SW_CTRL1", "COEX_STATUS1"], pin46: ["HOST_IRQ"], pin47: ["VSS"], pin48: ["IOVDD"], pin49: ["EP"],
};
const ncPins = ["RSV6", "NC21", "NC22", "NC23", "NC24", "COEX_GRANT", "SW_CTRL0"];
/** tied to GND per Revision 1 Errata [9] (floating, they raise IOVDD leakage) */
const nrf7002GroundedPins = ["RSV2", "RSV3", "RSV4", "RSV5", "QSPI_DATA2", "QSPI_DATA3", "COEX_STATUS0", "COEX_REQ", "SW_CTRL1"];
const Nrf7002 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "NRF7002-QFAA-R7", supplierPartNumbers: { jlcpcb: ["C5370744"] }, pinLabels: nrf7002Pins, internallyConnectedPins: [["VSS", "EP", "BUCKVSS1", "BUCKVSS2"]], footprint: jsx(Nrf7002Qfn48, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C5370744.obj?uuid=d0fbea2586a94bf4a0c0b2823af3d10c", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schWidth: 2.75, schHeight: 4.35, schPinArrangement: {
leftSide: { direction: "top-to-bottom", pins: ["VBAT", "AFEVBAT", "BUCKVBAT", "BUCKVBATS", "BUCKOUT", "PWRBUCKVDD", "RFBUCKVDD", "BUCKVMID", "IOVDD", "OTPVDD", "PWRIOVDD", "DIGVDD", "PALDO", "PAVDD0", "PAVDD1", "SXLDO", "RFVDD", "XOLDO", "AFELDO"] },
rightSide: { direction: "top-to-bottom", pins: ["SPI_CLK", "SPI_SS", "SPI_MOSI", "SPI_MISO", "HOST_IRQ", "BUCKEN", "TXRF0", "TXRF1", "XOP", "XON", "QSPI_DATA2", "QSPI_DATA3", "COEX_STATUS0", "COEX_REQ", "COEX_GRANT", "SW_CTRL0", "SW_CTRL1"] },
bottomSide: { direction: "left-to-right", pins: ["VSS", "EP", "BUCKVSS1", "BUCKVSS2"] },
topSide: { direction: "left-to-right", pins: ["RSV2", "RSV3", "RSV4", "RSV5", "RSV6", "NC21", "NC22", "NC23", "NC24"] },
}, pinAttributes: {
VBAT: { requiresPower: true }, IOVDD: { requiresPower: true }, VSS: { requiresGround: true }, EP: { requiresGround: true },
...Object.fromEntries(ncPins.map((p) => [p, { doNotConnect: true }])),
...Object.fromEntries(nrf7002GroundedPins.map((p) => [p, { requiresGround: true }])),
} }));
/** TDK DPX165950DT-8148A1 2.4 / 5 GHz WLAN diplexer, 1.6 x 0.8 mm, 6 terminals (JLC C307668, 6.7k in stock).
* Pins (JLC/EasyEDA symbol): 1 LOW_BAND (2.4 GHz), 3 HIGH_BAND (5 GHz), 5 COM (antenna), 2/4/6 GND.
* Land pattern = the EasyEDA one of C307668 (0.35 x 0.625 mm lands, 0.55 mm pitch, rows +/-0.54 mm; pins 1-3 on
* the lower row left to right, 4-6 on the upper row right to left), drawn explicitly because the matching
* dfn6 footprinter string renders with width and length swapped in this core. Plays the role of U2
* "2.4 / 5 GHz WLAN Dual Band Diplexer" in Nordic's nRF7002 reference schematic. */
const diplexerPins = { pin1: ["LOW_BAND"], pin2: ["GND3"], pin3: ["HIGH_BAND"], pin4: ["GND2"], pin5: ["COM"], pin6: ["GND1"] };
const Diplexer = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "DPX165950DT-8148A1", supplierPartNumbers: { jlcpcb: ["C307668"] }, pinLabels: diplexerPins, internallyConnectedPins: [["GND1", "GND2", "GND3"]], footprint: jsxs("footprint", { children: [[1, 2, 3].map((p, i) => pad(p, -0.55 + i * 0.55, -0.54, 0.35, 0.625)), [4, 5, 6].map((p, i) => pad(p, 0.55 - i * 0.55, 0.54, 0.35, 0.625)), outline(1.6, 0.8), courtyard(2.2, 2.0)] }), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C307668.obj?uuid=65fbddda7e9a4bb69de86e05fa1ddb6b", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["LOW_BAND", "HIGH_BAND", "GND1"] }, rightSide: { direction: "top-to-bottom", pins: ["COM", "GND2", "GND3"] } }, pinAttributes: { GND1: { requiresGround: true }, GND2: { requiresGround: true }, GND3: { requiresGround: true } } }));
/** 40 MHz crystal, 2016, CL 8 pF, ESR 30 ohm, +/-10 ppm (Hosonic/TKD K2B400000810, JLC C2835990, 20k in stock).
* Nordic: 40 MHz, CL = 8 pF, ESR <= 100 ohm; no external load capacitors (nRF7002 reference schematic X1). */
const crystalPins = { pin1: ["X1"], pin2: ["GND1"], pin3: ["X2"], pin4: ["GND2"] };
const Crystal40M = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "K2B400000810", supplierPartNumbers: { jlcpcb: ["C2835990"] }, pinLabels: crystalPins, footprint: jsx(Crystal2016, {}), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C2835990.obj?uuid=51ae9b24ba7a408881f7752b57b66e45", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schWidth: 0.6, schHeight: 1.15, schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["X1"] }, rightSide: { direction: "top-to-bottom", pins: ["X2"] }, bottomSide: { direction: "left-to-right", pins: ["GND1", "GND2"] } }, pinAttributes: { GND1: { requiresGround: true }, GND2: { requiresGround: true } } }));
/** Richtek RT9080-33GJ5 3.3 V / 600 mA LDO, TSOT-23-5 (JLC C841192, 67k in stock): 2 uA quiescent, VIN up to 5.5 V
* (VSYS follows VBUS while charging, so the nRF7002's 4.5 V VBAT maximum rules out feeding it from VSYS directly,
* and its 260 mA TX peak exceeds the nPM1300 bucks' 200 mA). Pins: 1 VIN, 2 GND, 3 EN, 4 NC, 5 VOUT. */
const rt9080Pins = { pin1: ["VIN"], pin2: ["GND"], pin3: ["EN"], pin4: ["NC"], pin5: ["VOUT"] };
const Rt9080 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "RT9080-33GJ5", supplierPartNumbers: { jlcpcb: ["C841192"] }, pinLabels: rt9080Pins, footprint: "sot25_w2.3mm_pw0.53mm_pl1.05mm_pin1location(bottomside,left)", cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C841192.obj?uuid=c7fdf6dae3ca4abaabd1bafd2d31350d", rotationOffset: { x: 0, y: 0, z: 90 }, positionOffset: { x: 0, y: 0, z: 0 } }, schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["VIN", "EN"] }, rightSide: { direction: "top-to-bottom", pins: ["VOUT", "NC"] }, bottomSide: { direction: "left-to-right", pins: ["GND"] } }, pinAttributes: { VIN: { requiresPower: true }, VOUT: { providesPower: true }, GND: { requiresGround: true }, NC: { doNotConnect: true } } }));
/** Nexperia NX3DV2567HR-Q100X four-pole double-throw switch, HXQFN16 3 x 3 mm (JLC C2652485; second source
* C52098293 NX3DV2567HR-TP has the same pin names in its EasyEDA symbol). Datasheet NX3DV2567-Q100 rev 1.1:
* 1 1Y0, 2 S, 3 2Y1, 4 2Z, 5 2Y0, 6 GND, 7 3Y1, 8 3Z, 9 3Y0, 10 n.c., 11 4Y1, 12 4Z, 13 4Y0, 14 VCC, 15 1Y1, 16 1Z.
* Switch 1 is the 0.5 ohm "supply" pole (SIM VCC), 2-4 the 7 ohm data poles. S = L -> nZ-nY0, S = H -> nZ-nY1.
* VCC 1.4-4.3 V. The same part switches SIM_1V8/RST/CLK/IO between the nano-SIM socket and the MFF2 eSIM on the
* nRF9151 DK (PCA10171 sheet 7). Land pattern: the EasyEDA footprint of C2652485 (0.28 x 0.80 mm pill lands,
* 0.5 mm pitch, 1.9 mm centre pad, tied to GND). */
const simSwitchPins = {
pin1: ["Y0_1"], pin2: ["S"], pin3: ["Y1_2"], pin4: ["Z2"], pin5: ["Y0_2"], pin6: ["GND"], pin7: ["Y1_3"], pin8: ["Z3"],
pin9: ["Y0_3"], pin10: ["NC"], pin11: ["Y1_4"], pin12: ["Z4"], pin13: ["Y0_4"], pin14: ["VCC"], pin15: ["Y1_1"], pin16: ["Z1"], pin17: ["EP"],
};
const pill = (pin, x, y, horizontal) => (jsx("smtpad", { portHints: [`pin${pin}`], pcbX: x, pcbY: y, width: horizontal ? 0.8 : 0.28, height: horizontal ? 0.28 : 0.8, radius: 0.14, shape: "pill" }, pin));
const SimSwitch = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "NX3DV2567HR-Q100X", supplierPartNumbers: { jlcpcb: ["C2652485"] }, pinLabels: simSwitchPins, internallyConnectedPins: [["GND", "EP"]], footprint: jsxs("footprint", { children: [[1, 2, 3, 4].map((p, i) => pill(p, -1.565, 0.75 - i * 0.5, true)), [5, 6, 7, 8].map((p, i) => pill(p, -0.75 + i * 0.5, -1.562, false)), [9, 10, 11, 12].map((p, i) => pill(p, 1.565, -0.75 + i * 0.5, true)), [13, 14, 15, 16].map((p, i) => pill(p, 0.75 - i * 0.5, 1.562, false)), pad(17, 0, 0, 1.9, 1.9), outline(3, 3), jsx("silkscreencircle", { pcbX: -1.95, pcbY: 1.3, radius: 0.12, strokeWidth: 0.1 }), courtyard(4.0, 4.0)] }), cadModel: { objUrl: "https://modelcdn.tscircuit.com/easyeda_models/assets/C2652485.obj?uuid=cff4e4db6da5413f8dddc79a50554a2a", rotationOffset: { x: 0, y: 0, z: 0 }, positionOffset: { x: 0, y: 0, z: 0 } }, schWidth: 0.9, schHeight: 1.7, schPinArrangement: {
leftSide: { direction: "top-to-bottom", pins: ["Z1", "Z4", "Z2", "Z3", "S", "VCC", "GND", "EP", "NC"] },
rightSide: { direction: "top-to-bottom", pins: ["Y0_1", "Y0_4", "Y0_2", "Y0_3", "Y1_1", "Y1_4", "Y1_2", "Y1_3"] },
}, pinAttributes: { VCC: { requiresPower: true }, GND: { requiresGround: true }, NC: { doNotConnect: true } } }));
/** MFF2 (ETSI TS 102 671, 5 x 6 mm SON-8, 1.27 mm pitch) embedded UICC / eSIM. The chip itself comes from the
* connectivity provider (1NCE, Onomondo, Velocity IoT, ...), it is not stocked by LCSC, so it is not placed by
* the assembler (doNotPlace) and is consigned or hand-soldered. Pin to contact mapping (TS 102 671 table 6.1, nRF9151
* DK U6 "MFFx_M2M_UICC"): 1 C5 GND, 2 C6 (VPP/SWP, n.c.), 3 C7 I/O, 4 C8 n.c., 5 C4 n.c., 6 C3 CLK, 7 C2 RST,
* 8 C1 VCC. Contacts b 0.40 x L 0.60 mm on the 6.00 mm sides; lands 0.60 x 1.00 mm centred 2.65 mm from the axis
* (TS 102 671 annex A: inner land edges 4.30 mm apart, outer 6.31 mm). The exposed heat feature is electrically
* insulated and gets no copper. Pin 1 (C5) is the top-left land, numbering counter-clockwise. */
const mff2Pins = {
pin1: ["GND", "C5"], pin2: ["C6"], pin3: ["IO", "C7"], pin4: ["C8"], pin5: ["C4"], pin6: ["CLK", "C3"], pin7: ["RST", "C2"], pin8: ["VCC", "C1"],
};
const EsimMff2 = (props) => (jsx("chip", { ...props, manufacturerPartNumber: "MFF2 eUICC (provider supplied)", pinLabels: mff2Pins, doNotPlace: true, footprint: jsxs("footprint", { children: [[1, 2, 3, 4].map((p, i) => pad(p, -2.65, 1.905 - i * 1.27, 1.0, 0.6)), [5, 6, 7, 8].map((p, i) => pad(p, 2.65, -1.905 + i * 1.27, 1.0, 0.6)), outline(6, 5), jsx("silkscreencircle", { pcbX: -3.55, pcbY: 2.55, radius: 0.15, strokeWidth: 0.1 }), courtyard(6.8, 5.4)] }), schWidth: 1.0, schHeight: 0.7, schPinArrangement: { leftSide: { direction: "top-to-bottom", pins: ["VCC", "RST", "CLK", "IO"] }, rightSide: { direction: "top-to-bottom", pins: ["C6", "C8", "C4"] }, bottomSide: { direction: "left-to-right", pins: ["GND"] } }, pinAttributes: { VCC: { requiresPower: true }, GND: { requiresGround: true }, C6: { doNotConnect: true }, C8: { doNotConnect: true }, C4: { doNotConnect: true } } }));
/** JLCPCB part numbers for the passive values used on the three boards (checked 2026-09-14
* against jlcsearch.tscircuit.com, re-checked 2026-09-23 for this board; see docs/bom.md). Keys are `${value}@${footprint}`. */
const JLC = {
// capacitors
"100nF@0402": "C1525", "1uF@0402": "C52923", "4.7uF@0402": "C23733", "10nF@0402": "C15195", "100pF@0402": "C1546",
"22pF@0402": "C1555", "1nF@0402": "C1523", "2.2nF@0402": "C2987940", "22nF@0402": "C107026", "39pF@0402": "C1563",
"10uF@0603": "C19702", "47uF@0805": "C2292827", "2.2uF@0603": "C23630", "10uF@0805": "C15850", "1uF@0603": "C15849",
"470nF@0603": "C1623", "100nF@0603": "C14663", "10nF@0603": "C57112", "22nF@0603": "C106222", "56nF@0603": "C282072",
"10uF@0402": "C15525", "2.2uF@0402": "C12530", "470nF@0402": "C106255", "220nF@0402": "C16772",
"100nF@0201": "C5142565", "10nF@0201": "C5142551", "22nF@0201": "C5142560", "220nF@0201": "C76936", "470nF@0201": "C2169138",
"1uF@0201": "C2846675", "2.2uF@0201": "C335106", "3.3uH@1008": "C98339", "22uF@0805": "C45783", "15nF@0603": "C107076",
// resistors
"10k@0402": "C25744", "330@0402": "C25104", "68k@0402": "C2909379", "100k@0402": "C25741", "47k@0402": "C25792", "1k@0402": "C11702", "0@0402": "C17168",
"1M@0402": "C26083", "20k@0402": "C25765", "68@0402": "C2909380", "200@0402": "C25087", "1.5k@0402": "C25867",
"33k@0402": "C25779", "3.3k@0402": "C2909345", "100k@0603": "C25803", "1k@0603": "C21190", "10k@0603": "C2906982",
"0.02@0805": "C601084", "5.1k@0402": "C25905", "2.2k@0402": "C25879", "330k@0402": "C25778",
// inductors / beads
"2.2uH@0806": "C337893", "1.5nH@0402": "C18221", "22nH@0402": "C12670", "9.1nH@0402": "C162547", "68nH@0402": "C108965",
"FB22R@0603": "C710389", "FB120R@0402": "C85812",
};
const jlcFor = (p, fp) => p.jlc ?? JLC[`${p.value}@${typeof fp === "string" ? fp : p.fpKey ?? "custom"}`];
const Cap = (p) => {
const fp = p.footprint === "0201" ? jsx(Cap0201, {}) : p.footprint ?? "0402";
const jlc = p.footprint === "0201" ? p.jlc ?? JLC[`${p.value}@0201`] : jlcFor(p, fp);
return (jsx("capacitor", { name: p.name, capacitance: p.value, footprint: fp, pcbX: p.x, pcbY: p.y, pcbRotation: p.rot ?? 0, layer: p.side ?? "top", schX: p.sch[0], schY: p.sch[1], schRotation: p.schRot ?? 0, schOrientation: p.schOrientation, schSectionName: p.section, doNotPlace: p.dnp, supplierPartNumbers: jlc ? { jlcpcb: [jlc] } : undefined }));
};
const Res = (p) => {
const fp = p.footprint ?? "0402";
const jlc = jlcFor(p, fp);
return (jsx("resistor", { name: p.name, resistance: p.value, footprint: fp, pcbX: p.x, pcbY: p.y, pcbRotation: p.rot ?? 0, layer: p.side ?? "top", schX: p.sch[0], schY: p.sch[1], schRotation: p.schRot ?? 0, schSectionName: p.section, doNotPlace: p.dnp, supplierPartNumbers: jlc ? { jlcpcb: [jlc] } : undefined }));
};
const Ind = (p) => {
const fp = p.footprint ?? "0402";
const jlc = jlcFor(p, fp);
return (jsx("inductor", { name: p.name, inductance: p.value, footprint: fp, pcbX: p.x, pcbY: p.y, pcbRotation: p.rot ?? 0, layer: p.side ?? "top", schX: p.sch[0], schY: p.sch[1], schRotation: p.schRot ?? 0, schSectionName: p.section, doNotPlace: p.dnp, supplierPartNumbers: jlc ? { jlcpcb: [jlc] } : undefined }));
};
/** Ferrite bead modelled as a chip so its value string ("22R@100MHz") is preserved in the BOM. */
const Bead = (p) => {
const fp = p.footprint ?? "0603";
return (jsx("chip", { name: p.name, manufacturerPartNumber: p.mpn, footprint: fp, pcbX: p.x, pcbY: p.y, pcbRotation: p.rot ?? 0, layer: p.side ?? "top", schX: p.sch[0], schY: p.sch[1], schRotation: p.schRot ?? 0, schSectionName: p.section, pinLabels: { pin1: ["A"], pin2: ["B"] }, schWidth: 0.6, schHeight: 1, schPinArrangement: { topSide: { direction: "left-to-right", pins: ["A"] }, bottomSide: { direction: "left-to-right", pins: ["B"] } }, supplierPartNumbers: p.jlc ? { jlcpcb: [p.jlc] } : undefined }));
};
function toLocal(p, centre, rotationDeg = 0) {
const dx = p.x - centre.x, dy = p.y - centre.y;
const a = (-rotationDeg * Math.PI) / 180;
const c = Math.cos(a), s = Math.sin(a);
return { x: +(dx * c - dy * s).toFixed(4), y: +(dx * s + dy * c).toFixed(4) };
}
/** Two tscircuit copper-pour traps, both of which leave a pour flooding over foreign copper (a short):
* 1. a pcbPath via only gets the layers between its from and to layer, and the pour solver cuts antipads on those
* layers alone, yet every via here is drilled through: a bottom->inner2 signal via would sit bare in the top and
* inner1 GND pours. So each via is authored as a full top->bottom via, followed (same spot) by a bottom->target
* step when the trace continues on another layer.
* 2. the pour solver only treats runs of consecutive *wire* points as trace obstacles; a via point ends the run, so a
* pad->via or via->next-point segment is invisible to it. A wire point is therefore added on the via, on both
* sides (zero-length hops, same copper). */
function throughVia(p) {
if (!p.via)
return [p];
const out = [{ x: p.x, y: p.y }, { x: p.x, y: p.y, via: true, fromLayer: "top", toLayer: "bottom" }];
if (p.toLayer && p.toLayer !== "bottom")
out.push({ x: p.x, y: p.y, via: true, fromLayer: "bottom", toLayer: p.toLayer });
out.push({ x: p.x, y: p.y });
return out;
}
const throughVias = (points) => points.flatMap(throughVia);
/** Convert a board-frame polyline (optionally with layer changes) into pcbPath entries (vias drilled through). */
function localPath(points, centre, rotationDeg = 0) {
return points.flatMap((p) => throughVia({ ...toLocal(p, centre, rotationDeg), ...(p.via ? { via: true, toLayer: p.toLayer } : {}) }));
}
/** Board-level layout constants shared by the circuit and the check scripts.
* Coordinates are millimetres, board centre = (0, 0), top view (+x right, +y up). */
const BOARD = { w: 44, h: 32 };
/** nRF9151 SiP centre. The SiP decoupling, LTE match and GNSS front end are placed as one block
* relative to this point; the offsets are the verified placement of the pixal-gps tracker, whose
* SiP sat at (-4.5, 1.0). `rel(x, y)` converts a pixal-gps board coordinate into this board. */
const U1 = { x: -9.5, y: 1.5 };
const PIXAL_U1 = { x: -4.5, y: 1.0 };
const rel = (x, y) => ({ x: +(x - PIXAL_U1.x + U1.x).toFixed(3), y: +(y - PIXAL_U1.y + U1.y).toFixed(3) });
/** Renders the generated ground mesh: one short stub + plane via per ground land, straight
* same-layer links for lands that had no free via spot, and a plain net connection for the
* rest (routed by the autorouter). Generated by scripts/gen-gnd-mesh.py from the placement
* build; regenerate after any placement change. */
function GndMeshTraces({ mesh, net = "GND", plane = "inner1", width = 0.25 }) {
return (jsxs(Fragment$1, { children: [mesh.stubs.map((s) => (jsx(Fragment, { children: jsx("trace", { from: s.port, to: `net.${net}`, thickness: width, pcbPath: [{ x: s.local[0], y: s.local[1] }, { x: s.local[0], y: s.local[1], via: true, toLayer: plane }] }) }, `stub-${s.port}`))), mesh.links.map((l) => (jsx(Fragment, { children: jsx("trace", { from: l.from, to: l.to, thickness: width, pcbPath: [] }) }, `link-${l.from}`))), mesh.unresolved.map((p) => (jsx(Fragment, { children: jsx("trace", { from: p, to: `net.${net}` }) }, `auto-${p}`)))] }));
}
function RoutedTraces({ routes }) {
return (jsx(Fragment$1, { children: routes.legs.map((l) => (jsx(Fragment, { children: jsx("trace", { name: l.id, from: l.from, to: l.to, thickness: l.width, pcbPath: localPath(l.path, l.fromCentre, l.fromRotation) }) }, l.id))) }));
}
var source = "0172668a0f0f881235c70928aa4047c9b4f3bd48008094cd0a4de07fb9e03b24";
var router = "Freerouting 1.9.0 (local, .tmp/router/index.ses)";
var legs = [
{
net: "GND",
from: "U2.GND_PAD",
to: "U2.GND_PAD",
width: 0.15,
path: [
{
x: -0.35,
y: -3.6
}
],
id: "fr_0_U2_GND_PAD",
fromCentre: {
x: 0.19999999999999996,
y: -3.6
},
fromRotation: 0
},
{
net: "ACC_INT1",
from: "U1.P0_10",
to: "U6.INT1",
width: 0.1,
path: [
{
x: -8.75,
y: 6.625
},
{
x: -8.75,
y: 7.4531
},
{
x: -10.4431,
y: 9.1462
},
{
x: -10.4431,
y: 9.5474
},
{
x: -10.6965,
y: 9.8008
},
{
x: -10.6965,
y: 10.5285
},
{
x: -10.475,
y: 10.75
}
],
id: "fr_1_U1_P0_10",
fromCentre: {
x: -9.5,
y: 1.4999999999999998
},
fromRotation: 0
},
{
net: "ACC_INT2",
from: "U1.P0_11",
to: "U6.INT2",
width: 0.1,
path: [
{
x: -9.25,
y: 6.625
},
{
x: -9.25,
y: 7.3454
},
{
x: -11.1565,
y: 9.2519
},
{
x: -11.1565,
y: 9.5473
},
{
x: -10.9032,
y: 9.8006
},
{
x: -10.9032,
y: 11.2285
},
{
x: -10.8817,
y: 11.25
},
{
x: -10.475,
y: 11.25
}
],
id: "fr_2_U1_P0_11",
fromCentre: {
x: -9.5,
y: 1.4999999999999998
},
fromRotation: 0
},
{
net: "BAT_NTC",
from: "RT1.A",
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],
local: [
0.025,
0.25
]
},
{
port: "U6.RES",
layer: "top",
pad: [
-8.85,
11.875
],
via: [
-8.85,
12.575
],
local: [
0.75,
1.575
]
},
{
port: "U6.GND2",
layer: "top",
pad: [
-9.35,
11.875
],
via: [
-9.35,
12.875
],
local: [
0.25,
1.875
]
},
{
port: "J4.SHELL1",
layer: "bottom",
pad: [
-15.05,
-11
],
via: [
-15.05,
-11.95
],
local: [
6.34,
0
]
},
{
port: "J4.SHELL2",
layer: "bottom",
pad: [
-15.05,
-0.22
],
via: [
-16.532,
0.452
],
local: [
-6.062,
-1.482
]
},
{
port: "U4.GND",
layer: "bottom",
pad: [
-18,
-13.3
],
via: [
-16.7,
-13.3
],
local: [
1.3,
0
]
},
{
port: "X1.GND1",
layer: "bottom",
pad: [
5.7,
10.35
],
via: [
4.8,
10.35
],
local: [
-1.6,
-0.55
]
},
{
port: "X1.GND2",
layer: "bottom",
pad: [
7.1,
11.45
],
via: [
8,
11.45
],
local: [
1.6,
0.55
]
},
{
port: "FL1.GND2",
layer: "top",
pad: [
11.34,
3.9
],
via: [
11.34,
3.275
],
local: [
1.175,
0.54
]
},
{
port: "J3.GND1",
layer: "top",
pad: [
14.225,
4.675
],
via: [
14.225,
5.65
],
local: [
-2.45,
0.475
]
},
{
port: "J3.GND2",
layer: "top",
pad: [
14.225,
1.725
],
via: [
14.225,
2.7
],
local: [
0.5,
0.475
]
},
{
port: "U8.GND",
layer: "bottom",
pad: [
-2.85,
-9.895
],
via: [
-3.8,
-9.895
],
local: [
1.7,
1.905
]
},
{
port: "J7.GND",
layer: "bottom",
pad: [
-6.67,
13.065
],
via: [
-6.67,
12.221
],
local: [
-1.27,
-1.479
]
},
{
port: "C4.pin2",
layer: "top",
pad: [
-17.45,
-1.99
],
via: [
-16.68,
-1.99
],
local: [
0.51,
-0.77
]
},
{
port: "C2.pin2",
layer: "top",
pad: [
-17.45,
1.51
],
via: [
-16.68,
1.51
],
local: [
0.51,
-0.77
]
},
{
port: "C3.pin2",
layer: "top",
pad: [
-20,
2.712
],
via: [
-20,
3.675
],
local: [
1.875,
0
]
},
{
port: "C1.pin2",
layer: "top",
pad: [
-19.9,
-2.275
],
via: [
-19.9,
-1.425
],
local: [
1.675,
0
]
},
{
port: "C5.pin2",
layer: "top",
pad: [
-5.1,
8.71
],
via: [
-5.1,
9.43
],
local: [
1.23,
0
]
},
{
port: "C6.pin2",
layer: "top",
pad: [
-6.2,
8.71
],
via: [
-6.2,
9.43
],
local: [
1.23,
0
]
},
{
port: "C7.pin1",
layer: "top",
pad: [
-12.75,
-6.21
],
via: [
-12.75,
-6.93
],
local: [
-1.23,
-0
]
},
{
port: "C8.pin2",
layer: "top",
pad: [
-17.45,
3.41
],
via: [
-17.45,
4.13
],
local: [
1.23,
0
]
},
{
port: "C9.pin1",
layer: "top",
pad: [
-17.45,
-5.21
],
via: [
-17.45,
-5.93
],
local: [
-1.23,
-0
]
},
{
port: "C11.pin2",
layer: "top",
pad: [
-5.24,
-7.35
],
via: [
-4.52,
-7.35
],
local: [
1.23,
0
]
},
{
port: "C14.pin2",
layer: "top",
pad: [
-0.9,
-9.61
],
via: [
-0.9,
-10.33
],
local: [
1.23,
0
]
},
{
port: "C15.pin2",
layer: "top",
pad: [
0.1,
-9.61
],
via: [
0.1,
-10.33
],
local: [
1.23,
0
]
},
{
port: "C16.pin2",
layer: "top",
pad: [
2.1,
-9.61
],
via: [
2.1,
-10.33
],
local: [
1.23,
0
]
},
{
port: "C17.pin2",
layer: "top",
pad: [
3.1,
-9.61
],
via: [
3.1,
-10.33
],
local: [
1.23,
0
]
},
{
port: "C18.pin2",
layer: "top",
pad: [
5.11,
-2.1
],
via: [
5.83,
-2.1
],
local: [
1.23,
0
]
},
{
port: "R5.pin2",
layer: "top",
pad: [
-2.9,
-9.61
],
via: [
-2.037,
-10.437
],
local: [
1.337,
0.863
]
},
{
port: "C21.pin2",
layer: "bottom",
pad: [
17.025,
-4.25
],
via: [
17.875,
-4.25
],
local: [
-1.675,
-0
]
},
{
port: "C23.pin2",
layer: "bottom",
pad: [
21.35,
-3.91
],
via: [
21.35,
-4.63
],
local: [
-1.23,
-0
]
},
{
port: "C24.pin2",
layer: "bottom",
pad: [
12.3,
1.525
],
via: [
11.375,
1.525
],
local: [
-0.825,
0.925
]
},
{
port: "C26.pin2",
layer: "bottom",
pad: [
12.075,
-3.9
],
via: [
11.225,
-3.9
],
local: [
-1.675,
0
]
},
{
port: "C27.pin2",
layer: "bottom",
pad: [
16.75,
5.51
],
via: [
16.75,
6.38
],
local: [
-1.38,
-0
]
},
{
port: "C29.pin2",
layer: "bottom",
pad: [
18.65,
4.49
],
via: [
19.42,
4.49
],
local: [
-0.51,
-0.77
]
},
{
port: "C30.pin2",
layer: "top",
pad: [
-11.6,
11.51
],
via: [
-11.6,
12.23
],
local: [
1.23,
0
]
},
{
port: "C32.pin2",
layer: "bottom",
pad: [
-20.51,
1.2
],
via: [
-21.23,
1.2
],
local: [
-1.23,
0
]
},
{
port: "R10.pin2",
layer: "top",
pad: [
-11.2,
14.91
],
via: [
-10.43,
14.91
],
local: [
0.51,
-0.77
]
},
{
port: "C41.pin2",
layer: "top",
pad: [
2.95,
9.26
],
via: [
2.95,
9.98
],
local: [
1.23,
0
]
},
{
port: "C42.pin2",
layer: "top",
pad: [
1.3,
10.26
],
via: [
2.07,
10.26
],
local: [
0.51,
-0.77
]
},
{
port: "C47.pin2",
layer: "bottom",
pad: [
0.27,
1.3
],
via: [
-0.41,
1.3
],
local: [
-1.01,
0
]
},
{
port: "C44.pin2",
layer: "bottom",
pad: [
0.27,
4.3
],
via: [
-0.41,
4.3
],
local: [
-1.01,
0
]
},
{
port: "C50.pin2",
layer: "bottom",
pad: [
0.27,
3.3
],
via: [
-0.41,
3.3
],
local: [
-1.01,
0
]
},
{
port: "C49.pin2",
layer: "bottom",
pad: [
0.27,
2.3
],
via: [
-0.41,
2.3
],
local: [
-1.01,
0
]
},
{
port: "C43.pin2",
layer: "top",
pad: [
7.4,
10.63
],
via: [
8.05,
10.63
],
local: [
0.33,
-0.65
]
},
{
port: "C53.pin2",
layer: "top",
pad: [
7.8,
8.78
],
via: [
8.45,
8.78
],
local: [
0.33,
-0.65
]
},
{
port: "C46.pin2",
layer: "bottom",
pad: [
9.2,
8.49
],
via: [
9.2,
7.77
],
local: [
-1.23,
-0
]
},
{
port: "C56.pin2",
layer: "top",
pad: [
5.8,
8.78
],
via: [
5.128,
9.473
],
local: [
1.023,
0.672
]
},
{
port: "C45.pin2",
layer: "top",
pad: [
5,
8.78
],
via: [
4.35,
8.78
],
local: [
0.33,
0.65
]
},
{
port: "C54.pin2",
layer: "top",
pad: [
11.23,
6.45
],
via: [
11.91,
6.45
],
local: [
1.01,
0
]
},
{
port: "C51.pin2",
layer: "top",
pad: [
10.86,
7.3
],
via: [
11.58,
7.3
],
local: [
1.23,
0
]
},
{
port: "C57.pin2",
layer: "top",
pad: [
10.63,
2.2
],
via: [
11.31,
2.2
],
local: [
1.01,
0
]
},
{
port: "C58.pin2",
layer: "top",
pad: [
9.11,
0.3
],
via: [
9.83,
0.3
],
local: [
1.23,
0
]
},
{
port: "C59.pin2",
layer: "bottom",
pad: [
15.2,
11.09
],
via: [
15.2,
10.37
],
local: [
-1.23,
-0
]
},
{
port: "C60.pin2",
layer: "bottom",
pad: [
10,
11.09
],
via: [
10,
10.37
],
local: [
-1.23,
-0
]
},
{
port: "C33.pin2",
layer: "bottom",
pad: [
-13.9,
-14.81
],
via: [
-13.13,
-14.81
],
local: [
-0.51,
-0.77
]
},
{
port: "C34.pin2",
layer: "bottom",
pad: [
-6.01,
-15
],
via: [
-6.73,
-15
],
local: [
-1.23,
0
]
},
{
port: "R11.pin2",
layer: "bottom",
pad: [
-15.3,
-14.81
],
via: [
-16.07,
-14.81
],
local: [
-0.51,
0.77
]
},
{
port: "R12.pin2",
layer: "bottom",
pad: [
-0.6,
5.09
],
via: [
0.17,
5.09
],
local: [
-0.51,
-0.77
]
},
{
port: "R13.pin2",
layer: "bottom",
pad: [
12.09,
14.3
],
via: [
11.37,
14.3
],
local: [
-1.23,
0
]
}
];
var links = [
{
from: "U1.GND_71",
to: "U1.GND_112",
layer: "top",
a: [
-9.75,
6.625
],
b: [
-9.5,
5.075
]
},
{
from: "C31.pin2",
to: "U6.GND1",
layer: "top",
a: [
-7.7,
11.51
],
b: [
-8.725,
11.25
]
}
];
var unresolved = [
"U1.GND_13",
"U1.GND_15",
"U1.GND_34",
"U2.GND2",
"U2.GND3",
"U2.GND4",
"U3.PVSS2",
"J4.C5",
"U5.BUCKVSS1",
"U5.BUCKVSS2",
"U5.VSS",
"U9.GND",
"FL1.GND3",
"FL1.GND1",
"U7.GND",
"U7.EP",
"C10.pin1",
"C20.pin2",
"C22.pin2",
"R6.pin2",
"C48.pin2",
"C55.pin2",
"C52.pin2"
];
var gndMeshJson = {
stubs: stubs,
links: links,
unresolved: unresolved
};
/**
* nRF9151 GPS tracker (kids / pets), Rev A. 44 x 32 mm, 4 layers (JLC04161H-7628), double-sided assembly.
*
* nRF9151 SiP (LTE-M / NB-IoT / GNSS + Cortex-M33) powered by an nPM1300 PMIC from a 1-cell LiPo on a
* JST-PH connector, charged from a USB-C (power only) receptacle. Nano-SIM socket and an MFF2 eSIM
* share the SiP's single SIM port through an NX3DV2567 switch. nRF7002 Wi-Fi companion for SSID
* scanning (indoor location). LIS2DW12 motion wake, SOS button on the PMIC's SHPHLD input, two
* status LEDs on the PMIC's LED sinks, SMD buzzer for find-me. Three U.FL ports: LTE, GNSS, Wi-Fi.
*
* Sources for every value: docs/ and research/.
*/
// Schematic section origins (schematic units).
const S = {
SIP: [0, 0], RF: [18, -4], SIM: [-22, -8], PWR: [0, -32], WIFI: [22, 16], MOTION: [-22, 10], UI: [22, -28], DEBUG: [-22, 20],
};
const sch = (sec, dx, dy) => [S[sec][0] + dx, S[sec][1] + dy];
const at = (x, y) => rel(x, y);
/** pcbX/pcbY props for a pixal-gps coordinate */
const pos = (x, y) => { const p = rel(x, y); return { pcbX: p.x, pcbY: p.y }; };
// ---------------------------------------------------------------------------------------
// nRF9151 block: decoupling, LTE match and GNSS front end (pixal-gps placement, shifted)
// ---------------------------------------------------------------------------------------
const sipCaps = [
// VDD input filter, Nordic nRF9151 reference topology (PS "Reference circuitry" + nWP056 "VDD"): C1, C2 1u and
// C3 47u on the source (VSYS) side of FB1, C4 10u between FB1 and the VDD pin. C4 is a 10 V 0402 (Nordic allows a
// smaller package) so it fits the slot beside FB1.B, 3.6 mm from U1.VDD. Nordic's figure calls the source-side net
// VDD_nRF; here that net is VSYS, and VDD_NRF is the short FB1.B -> U1.VDD side.
{ name: "C1", value: "1uF", footprint: "0603", ...at(-14.9, -3.6), rot: 90, sch: sch("PWR", 3.1, 6.4), section: "PWR", schRot: 270 },
{ name: "C2", value: "1uF", ...at(-12.45, 0.5), rot: 90, sch: sch("PWR", 4.4, 3.8), section: "PWR", schRot: 270 },
{ name: "C3", value: "47uF", footprint: "0805", ...at(-15, 1.3), rot: 90, sch: sch("PWR", 1.8, 6.4), section: "PWR", schRot: 270 },
{ name: "C4", value: "10uF", jlc: "C408132", ...at(-12.45, -3), rot: 90, sch: sch("SIP", -9.8, 2), section: "SIP", schRot: 270 },
{ name: "C5", value: "100nF", ...at(-0.1, 7.7), rot: 90, sch: sch("PWR", -5.2, 6.9), section: "PWR", schRot: 270 },
{ name: "C6", value: "4.7uF", ...at(-1.2, 7.7), rot: 90, sch: sch("PWR", -3.9, 6.9), section: "PWR", schRot: 270 },
{ name: "C7", value: "4.7uF", ...at(-7.75, -6.2), rot: 90, sch: sch("SIP", -9, -4), section: "SIP", schRot: 90 }, // DEC0: exactly 4.7 uF
{ name: "C8", value: "100nF", ...at(-12.45, 2.4), rot: 90, sch: sch("SIP", -9, 4), section: "SIP", schRot: 270 }, // nRESET
{ name: "C9", value: "100nF", ...at(-12.45, -5.2), rot: 90, sch: sch("SIP", -9.8, -2), section: "SIP", schRot: 90 }, // SIM_1V8
// LTE match reservation: shunt (DNP) - series 0R - shunt (DNP)
{ name: "C10", value: "22pF", ...at(-2.75, -5.3), rot: 0, sch: sch("RF", 2, 6), section: "RF", schRot: 90, dnp: true },
{ name: "C11", value: "22pF", ...at(-0.75, -7.85), rot: 0, sch: sch("RF", 6, 6), section: "RF", schRot: 270, dnp: true },
// GNSS front end (SKY65943-11, Nordic DK values)
{ name: "C12", value: "39pF", ...at(2.75, -3.1), rot: 0, sch: sch("RF", 6, -2), section: "RF", schOrientation: "vertical" },
{ name: "C13", value: "39pF", ...at(7.6, -5.5), rot: 0, sch: sch("RF", 12, 0), section: "RF", schOrientation: "vertical" },
{ name: "C14", value: "100nF", ...at(4.1, -9.6), rot: 270, sch: sch("RF", 4, -6), section: "RF", schRot: 270 },
{ name: "C15", value: "100pF", ...at(5.1, -9.6), rot: 270, sch: sch("RF", 6, -6), section: "RF", schRot: 270 },
{ name: "C16", value: "100nF", ...at(7.1, -9.6), rot: 270, sch: sch("RF", 10, -6), section: "RF", schRot: 270 },
{ name: "C17", value: "100pF", ...at(8.1, -9.6), rot: 270, sch: sch("RF", 12, -6), section: "RF", schRot: 270 },
{ name: "C18", value: "1uF", ...at(9.6, -2.6), rot: 0, sch: sch("RF", 14, 4), section: "RF", schRot: 270 }, // VANT (LSOUT1) at the bias-T
];
const sipRes = [
{ name: "R1", value: "10k", ...at(-5, 9.6), rot: 90, side: "bottom", sch: sch("SIP", -5, 4), section: "SIP", schRot: 270 }, // ENABLE -> VDD
{ name: "R2", value: "1k", ...at(-5, 7.5), rot: 90, side: "bottom", sch: sch("SIP", -5, 2), section: "SIP" }, // nRESET series
{ name: "R3", value: "0", ...at(-2.25, -6.8), rot: 90, sch: sch("RF", 4, 6), section: "RF" }, // LTE series element
{ name: "R4", value: "1k", ...at(3.1, -9.6), rot: 90, sch: sch("RF", 2, -6), section: "RF", schRot: 90 }, // COEX0 -> VEN
{ name: "R5", value: "100k", ...at(2.1, -9.6), rot: 270, sch: sch("RF", 0, -6), section: "RF", schRot: 270 }, // COEX0 pull-down
];
const sipInd = [
{ name: "L2", value: "9.1nH", ...at(5.45, -1.9), rot: 0, sch: sch("RF", 10.4, -3), section: "RF", schRot: 90 },
{ name: "L3", value: "68nH", ...at(9.05, -4.3), rot: 90, sch: sch("RF", 14, 2), section: "RF", dnp: true }, // active-antenna bias-T
];
// ---------------------------------------------------------------------------------------
// Power (nPM1300), user interface, motion sensor, SIM socket
// ---------------------------------------------------------------------------------------
const PMIC = { x: 17.0, y: 0.2 }; // bottom side, rotated 180: VBUS/VBAT/CC column faces the right edge
const pwrCaps = [
{ name: "C20", value: "2.2uF", x: 21.35, y: 0.4, rot: 90, side: "bottom", sch: sch("PWR", -8, -2), section: "PWR", schRot: 270 }, // VBAT
{ name: "C21", value: "10uF", footprint: "0603", x: 16.2, y: -4.25, rot: 180, side: "bottom", sch: sch("PWR", 4.4, 6.4), section: "PWR", schRot: 270 }, // VSYS, + land under VOUT2 (=VSYS)
{ name: "C22", value: "1uF", x: 21.35, y: -1.5, rot: 90, side: "bottom", sch: sch("PWR", -8, 2), section: "PWR", schRot: 270 }, // VBUS
{ name: "C23", value: "1uF", x: 21.35, y: -3.4, rot: 90, side: "bottom", sch: sch("PWR", -8, 4), section: "PWR", schRot: 270 }, // VBUSOUT (mandatory)
{ name: "C24", value: "10uF", footprint: "0603", x: 12.3, y: 2.35, rot: 90, side: "bottom", sch: sch("PWR", 1.8, 3.8), section: "PWR", schRot: 270 }, // PVDD
{ name: "C26", value: "10uF", footprint: "0603", x: 12.9, y: -3.9, rot: 0, side: "bottom", sch: sch("PWR", -2.6, 6.9), section: "PWR", schRot: 270 }, // VOUT1 1.8 V
{ name: "C27", value: "100nF", x: 16.75, y: 5.0, rot: 270, side: "bottom", sch: sch("PWR", -1.3, 6.9), section: "PWR", schRot: 270 }, // VDDIO
{ name: "C29", value: "100pF", x: 18.65, y: 5.0, rot: 90, side: "bottom", sch: sch("PWR", -10, -2), section: "PWR", schRot: 270 }, // NTC pin filter (<= 100 pF)
// LIS2DW12
{ name: "C30", value: "100nF", x: -11.6, y: 11.0, rot: 90, sch: sch("PWR", -5.2, 4.3), section: "PWR", schRot: 270 }, // VDD_IO
{ name: "C31", value: "10uF", x: -7.7, y: 11.0, rot: 90, sch: sch("PWR", -3.9, 4.3), section: "PWR", schRot: 270 }, // VDD
// nano-SIM VCC at the socket (DK C48)
{ name: "C32", value: "10nF", x: -20, y: 1.2, rot: 0, side: "bottom", sch: sch("SIM", 4, -4), section: "SIM", schRot: 270 },
];
const pwrRes = [
{ name: "R6", value: "47k", x: 21.35, y: 2.3, rot: 90, side: "bottom", sch: sch("PWR", -6, -6), section: "PWR", schRot: 270 }, // VSET1 = 1.8 V
{ name: "R8", value: "10k", x: 17.7, y: 5.0, rot: 90, side: "bottom", sch: sch("PWR", -2, -6), section: "PWR", schRot: 90 }, // SDA pull-up
{ name: "R9", value: "10k", x: 15.8, y: 5.0, rot: 90, side: "bottom", sch: sch("PWR", 0, -8), section: "PWR", schRot: 90 }, // SCL pull-up
{ name: "R10", value: "100k", x: -11.2, y: 14.4, rot: 90, sch: sch("UI", 2, -4), section: "UI", schRot: 270 }, // buzzer gate pull-down
];
const pwrInd = [
{ name: "L1", value: "2.2uH", footprint: jsx(Ind0806, {}), fpKey: "0806", x: 12.1, y: -0.8, rot: 90, side: "bottom", sch: sch("PWR", 6, -2), section: "PWR" }, // BUCK1
];
// ---------------------------------------------------------------------------------------
// Wi-Fi locating: nRF7002 (Nordic reference schematic, PS v1.2 figure 19; C41..C58 = Nordic C1..C18)
// ---------------------------------------------------------------------------------------
const U5 = { x: 6.0, y: 4.4 }; // nRF7002 centre (top), rotated 90: RF pins (1-12) face +x, XO/LDO pins (13-24) +y,
// buck pins (25-36) -x, SPI (37-38, 35-36) and HOST_IRQ toward the SiP at the lower left.
const wifiCaps = [
// buck side (left)
{ name: "C41", value: "4.7uF", x: 2.95, y: 8.75, rot: 90, sch: sch("WIFI", -1.2, 6.9), section: "WIFI", schRot: 270 }, // BUCKVBAT (25)
{ name: "C42", value: "4.7uF", x: 1.3, y: 9.75, rot: 90, sch: sch("WIFI", -6.2, 2.9), section: "WIFI", schRot: 270 }, // VDD_BUCK at L5
{ name: "C48", value: "10nF", footprint: "0201", x: 2.1, y: 5.2, rot: 90, sch: sch("WIFI", -10, -2), section: "WIFI", schRot: 270 }, // BUCKVMID (29); its ground end ties to BUCKVSS (28)
{ name: "C47", value: "2.2uF", footprint: "0201", x: 0.6, y: 1.3, rot: 0, side: "bottom", sch: sch("WIFI", 0.1, 6.9), section: "WIFI", schRot: 270 }, // BUCKVBATS (31)
{ name: "C44", value: "470nF", footprint: "0201", x: 0.6, y: 4.3, rot: 0, side: "bottom", sch: sch("WIFI", -4.9, 2.9), section: "WIFI", schRot: 270 }, // PWRBUCKVDD (32, land y=3.8: caps follow the land order so the escapes don't cross)
{ name: "C50", value: "1uF", footprint: "0201", x: 0.6, y: 3.3, rot: 0, side: "bottom", sch: sch("WIFI", -4, 8), section: "WIFI", schRot: 270 }, // DIGVDD (33)
{ name: "C49", value: "2.2uF", footprint: "0201", x: 0.6, y: 2.3, rot: 0, side: "bottom", sch: sch("WIFI", -6, 8), section: "WIFI", schRot: 270 }, // PWRIOVDD (34, land y=3.0)
// XO / LDO side (top)
{ name: "C55", value: "2.2uF", footprint: "0201", x: 7.0, y: 8.45, rot: 90, sch: sch("WIFI", 10, 0), section: "WIFI", schRot: 270 }, // XOLDO (16)
{ name: "C43", value: "220nF", footprint: "0201", x: 7.4, y: 10.3, rot: 90, sch: sch("WIFI", -3.6, 2.9), section: "WIFI", schRot: 270 }, // RFBUCKVDD (15), at the top of the pin-15 channel
{ name: "C53", value: "22nF", footprint: "0201", x: 7.8, y: 8.45, rot: 90, sch: sch("WIFI", 10, -3), section: "WIFI", schRot: 270 }, // RFVDD (14), straight above the pin
{ name: "C46", value: "4.7uF", x: 9.2, y: 9.0, rot: 90, side: "bottom", sch: sch("WIFI", 1.4, 6.9), section: "WIFI", schRot: 270 }, // VBAT (13), bottom as in Nordic's layout
{ name: "C56", value: "1uF", footprint: "0201", x: 5.8, y: 8.45, rot: 90, sch: sch("WIFI", 10.8, 2), section: "WIFI", schRot: 270 }, // AFELDO (19)
{ name: "C45", value: "1uF", footprint: "0201", x: 5.0, y: 8.45, rot: 90, sch: sch("WIFI", -1.2, 4.3), section: "WIFI", schRot: 270 }, // AFEVBAT (20)
// RF side (right)
{ name: "C52", value: "100nF", footprint: "0201", x: 10.1, y: 5.85, rot: 0, sch: sch("WIFI", 0, -8), section: "WIFI", schRot: 270 }, // PAVDD0 (10)
{ name: "C54", value: "470nF", footprint: "0201", x: 10.9, y: 6.45, rot: 0, sch: sch("WIFI", 4, -8), section: "WIFI", schRot: 270 }, // SXLDO (11)
{ name: "C51", value: "4.7uF", x: 10.35, y: 7.3, rot: 0, sch: sch("WIFI", 2, -8), section: "WIFI", schRot: 270 }, // PALDO / PAVDD (12, 10, 8)
{ name: "C57", value: "100nF", footprint: "0201", x: 10.3, y: 2.2, rot: 0, sch: sch("WIFI", -6, -8), section: "WIFI", schRot: 270 }, // OTPVDD (1)
// host side (bottom)
{ name: "C58", value: "2.2uF", x: 8.6, y: 0.3, rot: 0, sch: sch("WIFI", -10, -6), section: "WIFI", schRot: 270 }, // IOVDD (48)
// RT9080 3.3 V LDO (Wi-Fi VBAT, buzzer, antenna bias)
{ name: "C59", value: "1uF", x: 15.2, y: 11.6, rot: 90, side: "bottom", sch: sch("PWR", 3.1, 3.8), section: "PWR", schRot: 270 }, // LDO VIN
{ name: "C60", value: "2.2uF", x: 10.0, y: 11.6, rot: 90, side: "bottom", sch: sch("WIFI", 0.1, 4.3), section: "WIFI", schRot: 270 }, // LDO VOUT
// SIM switch / eSIM supplies
{ name: "C33", value: "100nF", x: -13.9, y: -14.3, rot: 90, side: "bottom", sch: sch("PWR", -2.6, 4.3), section: "PWR", schRot: 270 }, // switch VCC
{ name: "C34", value: "100nF", x: -5.5, y: -15, rot: 0, side: "bottom", sch: sch("SIM", 14, 4), section: "SIM", schRot: 270 }, // eSIM VCC
];
const wifiRes = [
{ name: "R11", value: "100k", x: -15.3, y: -14.3, rot: 90, side: "bottom", sch: sch("SIM", 10, -8), section: "SIM", schRot: 270 }, // SIM_SEL pull-down: nano-SIM by default
{ name: "R12", value: "100k", x: -0.6, y: 5.6, rot: 90, side: "bottom", sch: sch("WIFI", -14, 0), section: "WIFI", schRot: 270 }, // BUCKEN pull-down
{ name: "R13", value: "100k", x: 12.6, y: 14.3, rot: 0, side: "bottom", sch: sch("PWR", 16, -10), section: "PWR", schRot: 270 }, // LDO EN pull-down
];
const wifiInd = [
{ name: "L5", value: "3.3uH", footprint: jsx(Ind0806, {}), fpKey: "0806", jlc: "C50325850", x: 1.3, y: 7.35, rot: 90, sch: sch("WIFI", -12, 4), section: "WIFI" }, // nRF7002 buck (APLH2016-3R3M, 1.25 A, 250 mOhm)
];
// ---------------------------------------------------------------------------------------
// Grounds: every land on the GND net is declared (internally bonded groups do not give the
// other pins a net), see the memory note in docs/design.md.
// ---------------------------------------------------------------------------------------
const GND_LANDS = [
...nrf9151GndPins.map((p) => `U1.${p}`),
"U2.GND1", "U2.GND2", "U2.GND3", "U2.GND4", "U2.GND_PAD",
"J1.GND1", "J1.GND2", "J2.GND1", "J2.GND2",
"C1.pin2", "C2.pin2", "C3.pin2", "C4.pin2", "C5.pin2", "C6.pin2", "C7.pin1", "C8.pin2", "C9.pin1", "C10.pin1", "C11.pin2",
"C14.pin2", "C15.pin2", "C16.pin2", "C17.pin2", "C18.pin2", "R5.pin2",
// nPM1300: paddle + power grounds
"U3.AVSS", "U3.PVSS1", "U3.PVSS2",
"C20.pin2", "C21.pin2", "C22.pin2", "C23.pin2", "C24.pin2", "C26.pin2", "C27.pin2", "C29.pin2",
"J5.GND1", "J5.GND2", "J5.SHELL1", "J5.SHELL2", "J5.SHELL3", "J5.SHELL4", "J6.BAT_N", "SW1.B", "SW1.B2", "Q1.S", "R10.pin2", "RT1.B",
"U6.GND1", "U6.GND2", "U6.SDO", "U6.RES", "C30.pin2", "C31.pin2",
"J4.SHELL1", "J4.SHELL2", "J4.GND", "U4.GND", "C32.pin2", "J7.GND",
// Wi-Fi block, LDO, SIM switch, eSIM
"U5.VSS", "U5.EP", "U5.BUCKVSS1", "U5.BUCKVSS2", ...nrf7002GroundedPins.map((p) => `U5.${p}`), "FL1.GND1", "FL1.GND2", "FL1.GND3", "J3.GND1", "J3.GND2", "X1.GND1", "X1.GND2",
...["C41", "C42", "C43", "C44", "C45", "C46", "C47", "C48", "C49", "C50", "C51", "C52", "C53", "C54", "C55", "C56", "C57", "C58", "C59", "C60", "C33", "C34"].map((c) => `${c}.pin2`),
"U9.GND", "R11.pin2", "R12.pin2", "R13.pin2", "U7.GND", "U7.EP", "U8.GND",
];
// The native autorouter is opt-in: KT_AUTOROUTE=1 npx tsci build index.circuit.tsx
const nativeAutoroute = typeof process !== "undefined" && process.env?.KT_AUTOROUTE === "1";
var index_circuit = () => (jsxs("board", { width: BOARD.w, height: BOARD.h, layers: 4, thickness: 1.6, borderRadius: 2, routingDisabled: !nativeAutoroute, title: "nRF9151 GPS tracker / nRF9151 + nRF7002 + nPM1300 / Rev A", fabricatorPreset: "jlcpcb_standard", minTraceWidth: 0.1, minTraceToPadEdgeClearance: 0.1, minPadEdgeToPadEdgeClearance: 0.1, minViaHoleDiameter: 0.2, minViaPadDiameter: 0.4, minBoardEdgeClearance: 0.3, pcbStyle: { viaHoleDiameter: "0.2mm", viaPadDiameter: "0.4mm" }, defaultTraceWidth: 0.15, doubleSidedAssembly: true, children: [jsx("autoroutingphase", { minTraceToPadEdgeClearance: "0.16mm", minViaEdgeToPadEdgeClearance: "0.2mm" }), Object.keys(S).map((name) => jsx(Fragment, { children: jsx("schematicsection", { name: name, displayName: name }) }, name)), jsx("net", { name: "GND", isGroundNet: true }), jsx("net", { name: "VSYS", isPowerNet: true, nominalTraceWidth: 0.4 }), jsx("net", { name: "VBAT", isPowerNet: true, nominalTraceWidth: 0.4 }), jsx("net", { name: "VBUS", isPowerNet: true, nominalTraceWidth: 0.4 }), jsx("net", { name: "V1V8", isPowerNet: true, nominalTraceWidth: 0.25 }), jsx("net", { name: "V3V3", isPowerNet: true, nominalTraceWidth: 0.3 }), jsx("net", { name: "VDD_NRF", isPowerNet: true, nominalTraceWidth: 0.4 }), jsx(Nrf9151, { name: "U1", pcbX: U1.x, pcbY: U1.y, schX: S.SIP[0], schY: S.SIP[1], schSectionName: "SIP" }), jsx(Bead, { name: "FB1", value: "22R", mpn: "BLM18SD220SN1D", jlc: "C710389", ...at(-12.9, -1.25), rot: 0, sch: sch("SIP", -11, 1), section: "SIP" }), jsx("trace", { from: "FB1.A", to: "net.VSYS" }), jsx("trace", { from: "FB1.B", to: "net.VDD_NRF" }), jsx("trace", { from: "U1.VDD", to: "net.VDD_NRF" }), jsx("trace", { from: "C1.pin1", to: "net.VSYS" }), jsx("trace", { from: "C2.pin1", to: "net.VSYS" }), jsx("trace", { from: "C3.pin1", to: "net.VSYS" }), jsx("trace", { from: "C4.pin1", to: "net.VDD_NRF" }), jsx("trace", { from: "R1.pin1", to: "net.VDD_NRF" }), jsx("trace", { from: "R1.pin2", to: "U1.ENABLE" }), jsx("trace", { from: "U1.VDD_GPIO", to: "net.V1V8" }), jsx("trace", { from: "C5.pin1", to: "net.V1V8" }), jsx("trace", { from: "C6.pin1", to: "net.V1V8" }), jsx("trace", { from: "U1.DEC0", to: "net.DEC0" }), jsx("trace", { from: "C7.pin2", to: "net.DEC0" }), jsx("trace", { from: "U1.nRESET", to: "net.NRESET" }), jsx("trace", { from: "C8.pin1", to: "net.NRESET" }), jsx("trace", { from: "R2.pin2", to: "net.NRESET" }), jsx("trace", { from: "R2.pin1", to: "net.RESET_TP" }), jsx("trace", { from: "U1.SWDIO", to: "net.SWDIO" }), jsx("trace", { from: "U1.SWDCLK", to: "net.SWDCLK" }), jsx("trace", { from: "U1.SIM_1V8", to: "net.SIM_1V8" }), jsx("trace", { from: "C9.pin2", to: "net.SIM_1V8" }), jsx("trace", { from: "U1.SIM_RST", to: "net.SIM_RST" }), jsx("trace", { from: "U1.SIM_CLK", to: "net.SIM_CLK" }), jsx("trace", { from: "U1.SIM_IO", to: "net.SIM_IO" }), jsx(Ufl, { name: "J1", ...pos(-2.25, -10), pcbRotation: 180, schX: S.RF[0] + 8, schY: S.RF[1] + 8, schSectionName: "RF" }), jsx("trace", { name: "rf_ant_1", from: "U1.ANT", to: "C10.pin2", thickness: 0.32, pcbPath: [] }), jsx("trace", { name: "rf_ant_2", from: "C10.pin2", to: "R3.pin2", thickness: 0.32, pcbPath: [] }), jsx("trace", { name: "rf_ant_3", from: "R3.pin1", to: "J1.SIG", thickness: 0.32, pcbPath: [] }), jsx("trace", { name: "rf_ant_4", from: "C11.pin1", to: "R3.pin1", thickness: 0.32, pcbPath: localPath([at(-2.25, -7.85)], at(-0.75, -7.85), 0) }), jsx(Sky65943, { name: "U2", ...pos(5.2, -4.1), schX: S.RF[0] + 8, schY: S.RF[1] - 3, schSectionName: "RF" }), jsx(Ufl, { name: "J2", ...pos(11.2, -5.8), pcbRotation: 270, schX: S.RF[0] + 16, schY: S.RF[1], schSectionName: "RF" }), jsx("trace", { name: "rf_gps_1", from: "U1.GPS", to: "C12.pin1", thickness: 0.32, pcbPath: [] }), jsx("trace", { name: "rf_gps_2", from: "C12.pin2", to: "U2.RF_OUT", thickness: 0.32, pcbPath: [] }), jsx("trace", { from: "U2.AMP_IN", to: "L2.pin1" }), jsx("trace", { from: "U2.FILT_OUT", to: "L2.pin2" }), jsx("trace", { name: "rf_gnss_in_1", from: "U2.RF_IN", to: "C13.pin1", thickness: 0.32, pcbPath: [] }), jsx("trace", { name: "rf_gnss_in_2", from: "C13.pin2", to: "J2.SIG", thickness: 0.32, pcbPath: [] }), jsx("trace", { name: "rf_bias_stub", from: "L3.pin1", to: "J2.SIG", thickness: 0.25, pcbPath: localPath([at(9.05, -5.638)], at(9.05, -4.3), 90) }), jsx("trace", { from: "L3.pin2", to: "net.VANT" }), jsx("trace", { from: "C18.pin1", to: "net.VANT" }), jsx("trace", { name: "lna_gnd2", from: "U2.GND2", to: "U2.GND_PAD", thickness: 0.25, pcbPath: localPath([at(5.7, -4.6)], at(5.2, -4.1), 0) }), jsx("trace", { name: "lna_gnd3", from: "U2.GND3", to: "U2.GND_PAD", thickness: 0.25, pcbPath: localPath([at(6.0, -3.6)], at(5.2, -4.1), 0) }), jsx("trace", { name: "lna_gnd4", from: "U2.GND4", to: "U2.GND_PAD", thickness: 0.25, pcbPath: localPath([at(4.7, -3.8)], at(5.2, -4.1), 0) }), jsx("trace", { from: "U1.COEX0", to: "net.COEX0" }), jsx("trace", { from: "R5.pin1", to: "net.COEX0" }), jsx("trace", { from: "R4.pin1", to: "net.COEX0" }), jsx("trace", { from: "R4.pin2", to: "net.LNA_VEN" }), jsx("trace", { from: "U2.VEN", to: "net.LNA_VEN" }), jsx("trace", { from: "C14.pin1", to: "net.LNA_VEN" }), jsx("trace", { from: "C15.pin1", to: "net.LNA_VEN" }), jsx(Bead, { name: "FB2", value: "120R", mpn: "BLM15AG121SN1D", jlc: "C85812", footprint: "0402", ...at(6.1, -9.6), rot: 90, sch: sch("RF", 8, -6), section: "RF" }), jsx("trace", { from: "FB2.A", to: "net.V1V8" }), jsx("trace", { from: "FB2.B", to: "net.LNA_VCC" }), jsx("trace", { from: "U2.VCC", to: "net.LNA_VCC" }), jsx("trace", { from: "C16.pin1", to: "net.LNA_VCC" }), jsx("trace", { from: "C17.pin1", to: "net.LNA_VCC" }), jsx(Npm1300, { name: "U3", pcbX: PMIC.x, pcbY: PMIC.y, pcbRotation: 180, layer: "bottom", schX: S.PWR[0], schY: S.PWR[1], schSectionName: "PWR" }), jsx(UsbC6p, { name: "J5", pcbX: 18.3, pcbY: -10, pcbRotation: 90, schX: S.PWR[0] - 16, schY: S.PWR[1], schSectionName: "PWR" }), jsx("trace", { from: "J5.VBUS1", to: "net.VBUS" }), jsx("trace", { from: "J5.VBUS2", to: "net.VBUS" }), jsx("trace", { from: "J5.CC1", to: "U3.CC1" }), jsx("trace", { from: "J5.CC2", to: "U3.CC2" }), jsx("trace", { from: "U3.VBUS", to: "net.VBUS" }), jsx("trace", { from: "C22.pin1", to: "net.VBUS" }), jsx("trace", { from: "U3.VBUSOUT", to: "net.VBUSOUT" }), jsx("trace", { from: "C23.pin1", to: "net.VBUSOUT" }), jsx(JstPh2, { name: "J6", pcbX: 13.9, pcbY: 10.3, pcbRotation: 90, schX: S.PWR[0] - 16, schY: S.PWR[1] - 6, schSectionName: "PWR" }), jsx("trace", { from: "J6.BAT_P", to: "net.VBAT" }), jsx("trace", { from: "U3.VBAT", to: "net.VBAT" }), jsx("trace", { from: "C20.pin1", to: "net.VBAT" }), jsx("chip", { name: "RT1", manufacturerPartNumber: "NCP15XH103F03RC", supplierPartNumbers: { jlcpcb: ["C77131"] }, footprint: "0402", pcbX: 20.4, pcbY: 6.2, pcbRotation: 0, layer: "bottom", pinLabels: { pin1: ["A"], pin2: ["B"] }, schX: S.PWR[0] - 12, schY: S.PWR[1] - 8, schSectionName: "PWR", schWidth: 0.6, schHeight: 1, schPinArrangement: { topSide: { direction: "left-to-right", pins: ["A"] }, bottomSide: { direction: "left-to-right", pins: ["B"] } } }), jsx("trace", { from: "U3.NTC", to: "net.BAT_NTC" }), jsx("trace", { from: "RT1.A", to: "net.BAT_NTC" }), jsx("trace", { from: "C29.pin1", to: "net.BAT_NTC" }), jsx("trace", { from: "U3.VSYS", to: "net.VSYS" }), jsx("trace", { from: "C21.pin1", to: "net.VSYS" }), jsx("trace", { from: "U3.PVDD", to: "net.VSYS" }), jsx("trace", { from: "C24.pin1", to: "net.VSYS" }), jsx("trace", { from: "U3.SW1", to: "L1.pin1" }), jsx("trace", { from: "L1.pin2", to: "net.V1V8" }), jsx("trace", { from: "U3.VOUT1", to: "net.V1V8" }), jsx("trace", { from: "C26.pin1", to: "net.V1V8" }), jsx("trace", { from: "U3.VSET1", to: "R6.pin1" }), jsx("trace", { from: "R6.pin2", to: "net.GND" }), jsx("trace", { from: "U3.VOUT2", to: "net.VSYS" }), jsx("trace", { from: "U3.VSET2", to: "net.GND" }), jsx("trace", { from: "U3.LSIN1", to: "net.V3V3" }), jsx("trace", { from: "U3.LSOUT1", to: "net.VANT" }), jsx("trace", { from: "U3.LSIN2", to: "net.V1V8" }), jsx("trace", { from: "U3.LSOUT2", to: "net.WIFI_IOVDD" }), jsx("trace", { from: "U3.VDDIO", to: "net.V1V8" }), jsx("trace", { from: "C27.pin1", to: "net.V1V8" }), jsx("trace", { name: "pmic_vbat_cap", from: "U3.VBAT", to: "C20.pin1", thickness: 0.3, pcbPath: [] }), jsx("trace", { name: "pwr_vbat_feed", from: "C20.pin1", to: "J6.BAT_P", thickness: 0.4, pcbPath: throughVias([{ x: 0.51, y: 0.0 }, { x: 0.0857, y: 0.4243, via: true, toLayer: "top" }, { x: 0.5857, y: 0.85 }, { x: 1.6857, y: 2.95 }, { x: 1.6857, y: 3.55 }, { x: 2.8857, y: 4.75 }, { x: 5.6857, y: 6.05 }, { x: 8.9, y: 7.45 }]) }), jsx("trace", { name: "pmic_vsys_esc", from: "U3.VSYS", to: "net.VSYS", thickness: 0.3, pcbPath: localPath([{ x: 20.25, y: 0.45 }, { x: 20.25, y: 0.45, via: true, toLayer: "inner2" }], PMIC, 180) }), jsx("trace", { name: "pmic_vbus_cap", from: "U3.VBUS", to: "C22.pin1", thickness: 0.15, pcbPath: localPath([{ x: 20.35, y: -0.05 }, { x: 21.1, y: -0.8 }], PMIC, 180) }), jsx("trace", { name: "pmic_vbusout_cap", from: "U3.VBUSOUT", to: "C23.pin1", thickness: 0.15, pcbPath: localPath([{ x: 20.25, y: -0.6, via: true, toLayer: "inner2" }, { x: 20.6, y: -2.89, via: true, toLayer: "bottom" }], PMIC, 180) }), jsx("trace", { name: "pmic_vddio_cap", from: "U3.VDDIO", to: "C27.pin1", thickness: 0.15, pcbPath: [] }), jsx("trace", { name: "pmic_lsin2_esc", from: "U3.LSIN2", to: "net.V1V8", thickness: 0.15, pcbPath: localPath([{ x: 16.25, y: -3 }, { x: 16.25, y: -3, via: true, toLayer: "inner2" }], PMIC, 180) }), jsx("trace", { name: "pmic_lsout1_esc", from: "U3.LSOUT1", to: "net.VANT", thickness: 0.1, pcbPath: localPath([{ x: 16.75, y: -3.47 }, { x: 16.75, y: -3.47, via: true, toLayer: "inner2" }], PMIC, 180) }), jsx("trace", { name: "pmic_lsin1_esc", from: "U3.LSIN1", to: "net.V3V3", thickness: 0.15, pcbPath: localPath([{ x: 17.25, y: -3 }, { x: 17.25, y: -3, via: true, toLayer: "inner2" }], PMIC, 180) }), jsx("trace", { name: "pmic_avss_tie", from: "U3.AVSS", to: "U3.PVSS2", thickness: 0.2, pcbPath: localPath([{ x: 15.25, y: 0.95 }], PMIC, 180) }), jsx("trace", { name: "pmic_sda_fanout", from: "U3.SDA", to: "R8.pin1", thickness: 0.1, pcbPath: localPath([{ x: 17.2, y: 3.42, via: true, toLayer: "top" }, { x: 17.2, y: 6.35 }, { x: 17.7, y: 6.35, via: true, toLayer: "bottom" }], PMIC, 180) }), jsx("trace", { name: "pmic_scl_fanout", from: "U3.SCL", to: "R9.pin1", thickness: 0.1, pcbPath: localPath([{ x: 17.75, y: 3.39, via: true, toLayer: "inner2" }, { x: 15.8, y: 5.34 }, { x: 15.8, y: 6.3, via: true, toLayer: "bottom" }], PMIC, 180) }), [["C20", 0.4, -0.11], ["C22", -1.5, -2.01], ["R6", 2.3, 1.79]].map(([ref, cy, gy]) => (jsx(Fragment, { children: jsx("trace", { name: `gvia_${ref}`, from: `${ref}.pin2`, to: "net.GND", thickness: 0.2, pcbPath: localPath([{ x: 21.48, y: gy }, { x: 21.48, y: gy, via: true, toLayer: "inner1" }], { x: 21.35, y: cy }, 90) }) }, `edgevia-${ref}`))), jsx("trace", { from: "U3.SDA", to: "net.I2C_SDA" }), jsx("trace", { from: "U3.SCL", to: "net.I2C_SCL" }), jsx("trace", { from: "R8.pin1", to: "net.I2C_SDA" }), jsx("trace", { from: "R8.pin2", to: "net.V1V8" }), jsx("trace", { from: "R9.pin1", to: "net.I2C_SCL" }), jsx("trace", { from: "R9.pin2", to: "net.V1V8" }), jsx("trace", { from: "U3.GPIO0", to: "net.PMIC_INT" }), jsx("trace", { from: "U3.SHPHLD", to: "net.SHPHLD" }), jsx(TactSwitch, { name: "SW1", pcbX: 0.6, pcbY: 13.2, pcbRotation: 90, schX: S.UI[0], schY: S.UI[1], schSectionName: "UI" }), jsx("trace", { from: "SW1.A", to: "net.SHPHLD" }), jsx("led", { name: "D1", footprint: "0402", color: "red", pcbX: 3.6, pcbY: 15.0, pinLabels: { pin1: ["cathode"], pin2: ["anode"] }, schX: S.UI[0] + 4, schY: S.UI[1], schSectionName: "UI", supplierPartNumbers: { jlcpcb: ["C779449"] }, schRotation: 270 }), jsx("led", { name: "D2", footprint: "0402", color: "green", pcbX: 5.6, pcbY: 15.0, pinLabels: { pin1: ["cathode"], pin2: ["anode"] }, schX: S.UI[0] + 7, schY: S.UI[1], schSectionName: "UI", supplierPartNumbers: { jlcpcb: ["C688877"] }, schRotation: 270 }), jsx("trace", { from: "D1.anode", to: "net.VSYS" }), jsx("trace", { from: "D1.cathode", to: "U3.LED1" }), jsx("trace", { from: "D2.anode", to: "net.VSYS" }), jsx("trace", { from: "D2.cathode", to: "U3.LED2" }), jsx(Buzzer, { name: "BZ1", pcbX: -17.6, pcbY: 12.7, schX: S.UI[0], schY: S.UI[1] - 6, schSectionName: "UI" }), jsx(Dmg1012t, { name: "Q1", pcbX: -12.8, pcbY: 14.4, pcbRotation: 90, schX: S.UI[0] + 4, schY: S.UI[1] - 8, schSectionName: "UI" }), jsx(Rb521s30, { name: "D3", pcbX: -13, pcbY: 12.0, pcbRotation: 90, schX: S.UI[0] + 4, schY: S.UI[1] - 4, schSectionName: "UI" }), jsx("trace", { from: "BZ1.POS", to: "net.V3V3" }), jsx("trace", { from: "D3.K", to: "net.V3V3" }), jsx("trace", { from: "BZ1.NEG", to: "net.BUZ_DRV" }), jsx("trace", { from: "D3.A", to: "net.BUZ_DRV" }), jsx("trace", { from: "Q1.D", to: "net.BUZ_DRV" }), jsx("trace", { from: "Q1.G", to: "net.BUZ_PWM" }), jsx("trace", { from: "R10.pin1", to: "net.BUZ_PWM" }), jsx(Lis2dw12, { name: "U6", pcbX: -9.6, pcbY: 11.0, schX: S.MOTION[0], schY: S.MOTION[1], schSectionName: "MOTION" }), jsx("trace", { from: "U6.VDD", to: "net.V1V8" }), jsx("trace", { from: "U6.VDD_IO", to: "net.V1V8" }), jsx("trace", { from: "U6.CS", to: "net.V1V8" }), jsx("trace", { from: "U6.SCL", to: "net.I2C_SCL" }), jsx("trace", { from: "U6.SDA", to: "net.I2C_SDA" }), jsx("trace", { from: "U6.INT1", to: "net.ACC_INT1" }), jsx("trace", { from: "U6.INT2", to: "net.ACC_INT2" }), jsx("trace", { from: "C30.pin1", to: "net.V1V8" }), jsx("trace", { from: "C31.pin1", to: "net.V1V8" }), jsx(NanoSimSocket, { name: "J4", pcbX: -15.05, pcbY: -5.61, pcbRotation: 270, layer: "bottom", schX: S.SIM[0], schY: S.SIM[1], schSectionName: "SIM" }), jsx(Tpd3f303, { name: "U4", pcbX: -18, pcbY: -13.3, layer: "bottom", schX: S.SIM[0] + 6, schY: S.SIM[1], schSectionName: "SIM" }), jsx("trace", { from: "U4.DATA1_OUT", to: "J4.RST" }), jsx("trace", { from: "U4.CLK_OUT", to: "J4.CLK" }), jsx("trace", { from: "U4.DATA2_OUT", to: "J4.IO" }), jsx("trace", { from: "U4.VCC", to: "net.SIM0_VCC" }), jsx("trace", { from: "J4.VCC", to: "net.SIM0_VCC" }), jsx("trace", { from: "C32.pin1", to: "net.SIM0_VCC" }), jsx(Nrf7002, { name: "U5", pcbX: U5.x, pcbY: U5.y, pcbRotation: 90, schX: S.WIFI[0], schY: S.WIFI[1], schSectionName: "WIFI" }), jsx(Rt9080, { name: "U9", pcbX: 12.6, pcbY: 11.6, layer: "bottom", schX: S.PWR[0] + 16, schY: S.PWR[1] - 8, schSectionName: "PWR" }), jsx("trace", { from: "U9.VIN", to: "net.VSYS" }), jsx("trace", { from: "C59.pin1", to: "net.VSYS" }), jsx("trace", { from: "U9.EN", to: "net.V3V3_EN" }), jsx("trace", { from: "R13.pin1", to: "net.V3V3_EN" }), jsx("trace", { from: "U9.VOUT", to: "net.V3V3" }), jsx("trace", { from: "C60.pin1", to: "net.V3V3" }), jsx("trace", { from: "U5.VBAT", to: "net.V3V3" }), jsx("trace", { from: "C46.pin1", to: "net.V3V3" }), jsx("trace", { from: "U5.AFEVBAT", to: "net.V3V3" }), jsx("trace", { from: "C45.pin1", to: "net.V3V3" }), jsx("trace", { from: "U5.BUCKVBAT", to: "net.V3V3" }), jsx("trace", { from: "C41.pin1", to: "net.V3V3" }), jsx("trace", { from: "U5.BUCKVBATS", to: "net.V3V3" }), jsx("trace", { from: "C47.pin1", to: "net.V3V3" }), jsx("trace", { from: "U5.BUCKOUT", to: "L5.pin1" }), jsx("trace", { from: "L5.pin2", to: "net.W_VDD_BUCK" }), jsx("trace", { from: "C42.pin1", to: "net.W_VDD_BUCK" }), jsx("trace", { from: "U5.PWRBUCKVDD", to: "net.W_VDD_BUCK" }), jsx("trace", { from: "C44.pin1", to: "net.W_VDD_BUCK" }), jsx("trace", { from: "U5.RFBUCKVDD", to: "net.W_VDD_BUCK" }), jsx("trace", { from: "C43.pin1", to: "net.W_VDD_BUCK" }), jsx("trace", { from: "U5.BUCKVMID", to: "C48.pin1" }), jsx("trace", { from: "U5.PALDO", to: "net.W_PALDO" }), jsx("trace", { from: "U5.PAVDD0", to: "net.W_PALDO" }), jsx("trace", { from: "U5.PAVDD1", to: "net.W_PALDO" }), jsx("trace", { from: "C51.pin1", to: "net.W_PALDO" }), jsx("trace", { from: "C52.pin1", to: "net.W_PALDO" }), jsx("trace", { from: "U5.SXLDO", to: "C54.pin1" }), jsx("trace", { from: "U5.RFVDD", to: "C53.pin1" }), jsx("trace", { from: "U5.XOLDO", to: "C55.pin1" }), jsx("trace", { from: "U5.AFELDO", to: "C56.pin1" }), jsx("trace", { from: "U5.DIGVDD", to: "C50.pin1" }), jsx("trace", { from: "U5.PWRIOVDD", to: "net.W_PWRIOVDD" }), jsx("trace", { from: "U5.OTPVDD", to: "net.W_PWRIOVDD" }), jsx("trace", { from: "C49.pin1", to: "net.W_PWRIOVDD" }), jsx("trace", { from: "C57.pin1", to: "net.W_PWRIOVDD" }), jsx("trace", { from: "U5.IOVDD", to: "net.WIFI_IOVDD" }), jsx("trace", { from: "C58.pin1", to: "net.WIFI_IOVDD" }), jsx(Crystal40M, { name: "X1", pcbX: 6.4, pcbY: 10.9, layer: "bottom", schX: S.WIFI[0] + 8, schY: S.WIFI[1] - 2, schSectionName: "WIFI" }), jsx("trace", { name: "xtal_xop", from: "U5.XOP", to: "X1.X1", thickness: 0.12, pcbPath: localPath([{ x: 6.6, y: 9.9 }, { x: 6.8, y: 10.2, via: true, toLayer: "bottom" }], U5, 90) }), jsx("trace", { name: "xtal_xon", from: "U5.XON", to: "X1.X2", thickness: 0.12, pcbPath: localPath([{ x: 6.2, y: 9.35, via: true, toLayer: "bottom" }, { x: 6.4, y: 9.55 }, { x: 6.4, y: 11.45 }], U5, 90) }), jsx("trace", { from: "U5.SPI_CLK", to: "net.WIFI_SCK" }), jsx("trace", { from: "U5.SPI_SS", to: "net.WIFI_CS" }), jsx("trace", { from: "U5.SPI_MOSI", to: "net.WIFI_MOSI" }), jsx("trace", { from: "U5.SPI_MISO", to: "net.WIFI_MISO" }), jsx("trace", { from: "U5.HOST_IRQ", to: "net.WIFI_IRQ" }), jsx("trace", { name: "wifi_vss_tie", from: "U5.VSS", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 7.8, y: 2.3 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_rsv2", from: "U5.RSV2", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 8.1, y: 2.6 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_rsv3", from: "U5.RSV3", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 8.1, y: 3.0 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_rsv4", from: "U5.RSV4", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 8.1, y: 3.4 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_rsv5", from: "U5.RSV5", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 8.1, y: 3.8 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_qspi_data2", from: "U5.QSPI_DATA2", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 4.6, y: 2.3 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_qspi_data3", from: "U5.QSPI_DATA3", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 5.0, y: 2.3 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_coex_status0", from: "U5.COEX_STATUS0", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 5.4, y: 2.3 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_coex_req", from: "U5.COEX_REQ", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 5.8, y: 2.3 }], U5, 90) }), jsx("trace", { name: "wifi_gnd_sw_ctrl1", from: "U5.SW_CTRL1", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 7.0, y: 2.3 }], U5, 90) }), jsx("trace", { name: "wifi_bvss1_tie", from: "U5.BUCKVSS1", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 3.9, y: 5.8 }], U5, 90) }), jsx("trace", { name: "wifi_bvss2_tie", from: "U5.BUCKVSS2", to: "U5.EP", thickness: 0.15, pcbPath: localPath([{ x: 3.9, y: 5.4 }], U5, 90) }), jsx("trace", { name: "wifi_bvmid_gnd", from: "C48.pin2", to: "U5.BUCKVSS2", thickness: 0.12, pcbPath: [] }), jsx("trace", { name: "paldo_join", from: "U5.PAVDD1", to: "C51.pin1", thickness: 0.15, pcbPath: localPath([{ x: 9.63, y: 5.0, via: true, toLayer: "bottom" }, { x: 9.65, y: 5.8, via: true, toLayer: "inner2" }, { x: 9.84, y: 7.95, via: true, toLayer: "top" }], U5, 90) }), jsx("trace", { name: "pavdd0_c52", from: "U5.PAVDD0", to: "C52.pin1", thickness: 0.15, pcbPath: localPath([{ x: 9.65, y: 5.8 }], U5, 90) }), jsx("trace", { name: "rfbuckvdd_c43", from: "U5.RFBUCKVDD", to: "C43.pin1", thickness: 0.12, pcbPath: [] }), jsx("trace", { name: "gvia_C55", from: "C55.pin2", to: "net.GND", thickness: 0.12, pcbPath: localPath([{ x: 7.0, y: 9.4 }, { x: 7.0, y: 9.4, via: true, toLayer: "inner1" }], { x: 7.0, y: 8.45 }, 90) }), jsx("trace", { name: "gstub_FL1_GND3", from: "FL1.GND3", to: "net.GND", thickness: 0.12, pcbPath: [{ x: -0.875, y: 0.9755 }, { x: -0.875, y: 0.9755, via: true, toLayer: "inner1" }] }), jsx("trace", { from: "U5.BUCKEN", to: "net.WIFI_BUCKEN" }), jsx("trace", { from: "R12.pin1", to: "net.WIFI_BUCKEN" }), jsx(Diplexer, { name: "FL1", pcbX: 10.8, pcbY: 4.45, pcbRotation: 270, schX: S.WIFI[0] + 8, schY: S.WIFI[1] - 8, schSectionName: "WIFI" }), jsx(Ufl, { name: "J3", pcbX: 13.75, pcbY: 3.2, pcbRotation: 270, schX: S.WIFI[0] + 14, schY: S.WIFI[1] - 8, schSectionName: "WIFI" }), jsx("trace", { name: "wifi_tx24", from: "U5.TXRF0", to: "FL1.LOW_BAND", thickness: 0.2, pcbPath: localPath([{ x: 10.26, y: 5.4 }], U5, 90) }), jsx("trace", { name: "wifi_tx5", from: "U5.TXRF1", to: "FL1.HIGH_BAND", thickness: 0.2, pcbPath: localPath([{ x: 9.45, y: 4.6 }, { x: 9.85, y: 3.9 }], U5, 90) }), jsx("trace", { name: "rf_wifi_ant", from: "FL1.COM", to: "J3.SIG", thickness: 0.32, pcbPath: localPath([{ x: 11.9, y: 4.45 }, { x: 12.7, y: 3.65 }], { x: 10.8, y: 4.45 }, 270) }), jsx(SimSwitch, { name: "U7", pcbX: -11, pcbY: -12.6, layer: "bottom", schX: S.SIM[0] - 8, schY: S.SIM[1], schSectionName: "SIM" }), jsx("trace", { name: "simsw_gnd_tie", from: "U7.GND", to: "U7.EP", thickness: 0.15, pcbPath: [{ x: 0.25, y: -1.3 }] }), jsx("trace", { name: "gstub_U7_GND", from: "U7.GND", to: "net.GND", thickness: 0.12, pcbPath: [{ x: 0.3283, y: -0.9671 }, { x: 0.3283, y: -0.9671, via: true, toLayer: "inner1" }] }), jsx("trace", { from: "U7.VCC", to: "net.V1V8" }), jsx("trace", { from: "C33.pin1", to: "net.V1V8" }), jsx("trace", { from: "U7.S", to: "net.SIM_SEL" }), jsx("trace", { from: "R11.pin1", to: "net.SIM_SEL" }), jsx("trace", { from: "U7.Z1", to: "net.SIM_1V8" }), jsx("trace", { from: "U7.Z2", to: "net.SIM_CLK" }), jsx("trace", { from: "U7.Z3", to: "net.SIM_IO" }), jsx("trace", { from: "U7.Z4", to: "net.SIM_RST" }), jsx("trace", { from: "U7.Y0_1", to: "net.SIM0_VCC" }), jsx("trace", { from: "U7.Y0_2", to: "U4.CLK_IN" }), jsx("trace", { from: "U7.Y0_3", to: "U4.DATA2_IN" }), jsx("trace", { from: "U7.Y0_4", to: "U4.DATA1_IN" }), jsx(EsimMff2, { name: "U8", pcbX: -5.5, pcbY: -11.8, layer: "bottom", schX: S.SIM[0] + 14, schY: S.SIM[1], schSectionName: "SIM" }), jsx("trace", { from: "U7.Y1_1", to: "net.SIM1_VCC" }), jsx("trace", { from: "U8.VCC", to: "net.SIM1_VCC" }), jsx("trace", { from: "C34.pin1", to: "net.SIM1_VCC" }), jsx("trace", { from: "U7.Y1_2", to: "U8.CLK" }), jsx("trace", { from: "U7.Y1_3", to: "U8.IO" }), jsx("trace", { from: "U7.Y1_4", to: "U8.RST" }), jsx(Tc2030, { name: "J7", pcbX: -5.4, pcbY: 13.7, layer: "bottom", schX: S.DEBUG[0], schY: S.DEBUG[1], schSectionName: "DEBUG" }), jsx("trace", { from: "J7.VREF", to: "net.V1V8" }), jsx("trace", { from: "J7.SWDIO", to: "net.SWDIO" }), jsx("trace", { from: "J7.SWCLK", to: "net.SWDCLK" }), jsx("trace", { from: "J7.NRESET", to: "net.RESET_TP" }), jsx("trace", { from: "U1.P0_08", to: "net.I2C_SDA" }), jsx("trace", { from: "U1.P0_09", to: "net.I2C_SCL" }), jsx("trace", { from: "U1.P0_10", to: "net.ACC_INT1" }), jsx("trace", { from: "U1.P0_11", to: "net.ACC_INT2" }), jsx("trace", { from: "U1.P0_04", to: "net.BUZ_PWM" }), jsx("trace", { from: "U1.P0_03", to: "net.PMIC_INT" }), jsx("trace", { from: "U1.P0_28", to: "net.WIFI_SCK" }), jsx("trace", { from: "U1.P0_29", to: "net.WIFI_MOSI" }), jsx("trace", { from: "U1.P0_30", to: "net.WIFI_MISO" }), jsx("trace", { from: "U1.P0_31", to: "net.WIFI_CS" }), jsx("trace", { from: "U1.P0_00", to: "net.WIFI_IRQ" }), jsx("trace", { from: "U1.P0_01", to: "net.WIFI_BUCKEN" }), jsx("trace", { from: "U1.P0_02", to: "net.V3V3_EN" }), jsx("trace", { from: "U1.P0_25", to: "net.SIM_SEL" }), sipCaps.map((c) => jsx(Cap, { ...c }, c.name)), sipRes.map((r) => jsx(Res, { ...r }, r.name)), sipInd.map((l) => jsx(Ind, { ...l }, l.name)), pwrCaps.map((c) => jsx(Cap, { ...c }, c.name)), pwrRes.map((r) => jsx(Res, { ...r }, r.name)), pwrInd.map((l) => jsx(Ind, { ...l }, l.name)), wifiCaps.map((c) => jsx(Cap, { ...c }, c.name)), wifiRes.map((r) => jsx(Res, { ...r }, r.name)), wifiInd.map((l) => jsx(Ind, { ...l }, l.name)), GND_LANDS.map((p) => jsx(Fragment, { children: jsx("trace", { from: p, to: "net.GND" }) }, `gnd-${p}`)), jsx("trace", { name: "vsys_feeder", from: "C21.pin1", to: "FB1.A", thickness: 0.35, pcbPath: throughVias([{ x: 1.7, y: -0.15 }, { x: 1.7, y: -0.15, via: true, toLayer: "top" }, { x: 6.3, y: 0.25 }, { x: 8.1, y: 0.25 }, { x: 8.1, y: 0.25, via: true, toLayer: "bottom" }, { x: 19.1, y: 0.25 }, { x: 19.1, y: 0.25, via: true, toLayer: "top" }, { x: 20.5, y: 0.35 }, { x: 20.5, y: 0.35, via: true, toLayer: "bottom" }, { x: 20.4, y: -0.15 }, { x: 22.8, y: -1.85 }, { x: 24.5, y: -2.75 }, { x: 26.1, y: -2.85 }, { x: 28.5, y: -2.25 }, { x: 33.1, y: -1.75 }, { x: 34.8, y: -2.75 }, { x: 34.8, y: -2.75, via: true, toLayer: "top" }, { x: 34.925, y: -3.5 }]) }), jsx("trace", { name: "vsys_feeder_link", from: "U3.VSYS", to: "C21.pin1", thickness: 0.25, pcbPath: throughVias([{ x: -3.25, y: -0.25 }, { x: -3.25, y: -0.25, via: true, toLayer: "top" }, { x: -1.9, y: 2.7 }, { x: -1.8, y: 3.5 }, { x: 2.4, y: 5.5 }, { x: 2.4, y: 5.5, via: true, toLayer: "bottom" }, { x: 3.7, y: 5.5 }, { x: 3.7, y: 5.5, via: true, toLayer: "top" }, { x: 2.5, y: 4.3 }, { x: 2.5, y: 4.3, via: true, toLayer: "bottom" }, { x: 1.625, y: 4.45 }]) }), jsx("trace", { name: "maze_BZ1_NEG", from: "BZ1.NEG", to: "D3.A", thickness: 0.2, pcbPath: throughVias([{ x: 4.6, y: -0.05 }]) }), jsx("trace", { name: "maze_BZ1_POS", from: "BZ1.POS", to: "D3.K", thickness: 0.3, pcbPath: throughVias([{ x: 1.7, y: -2.4 }, { x: 3.3, y: -2.4 }, { x: 4.6, y: -1.35 }]) }), jsx("trace", { name: "maze_C2_pin1", from: "C2.pin1", to: "FB1.A", thickness: 0.2, pcbPath: throughVias([{ x: -1.75, y: 1.275 }]) }), jsx("trace", { name: "maze_U3_LED1", from: "U3.LED1", to: "D1.cathode", thickness: 0.1, pcbPath: throughVias([{ x: -1.4, y: 3.2 }, { x: -1.4, y: 3.2, via: true, toLayer: "top" }, { x: -0.5, y: 0.6 }, { x: -0.5, y: -1.4 }, { x: 1.4, y: -3.4 }, { x: 1.4, y: -3.4, via: true, toLayer: "inner2" }, { x: 3.2, y: -5.3 }, { x: 3.6, y: -6.7 }, { x: 6.5, y: -9.7 }, { x: 7.2, y: -9.8 }, { x: 8.9, y: -11.7 }, { x: 12.3, y: -11.6 }, { x: 12.3, y: -11.6, via: true, toLayer: "top" }, { x: 12.9, y: -11.2 }, { x: 13.3, y: -11.5 }, { x: 13.91, y: -14.8 }]) }), jsx(GndMeshTraces, { mesh: gndMeshJson }), jsx(RoutedTraces, { routes: routesJson }), jsx("copperpour", { name: "GND_L1", layer: "top", connectsTo: "net.GND", clearance: 0.25, boardEdgeMargin: 0.4 }), jsx("copperpour", { name: "GND_L2", layer: "inner1", connectsTo: "net.GND", clearance: 0.25, boardEdgeMargin: 0.4, unbroken: true }), jsx("copperpour", { name: "GND_L4", layer: "bottom", connectsTo: "net.GND", clearance: 0.25, boardEdgeMargin: 0.4 }), jsx("silkscreentext", { text: "NRF9151 GPS TRACKER REV A", pcbX: 2.5, pcbY: -14.6, fontSize: 0.8, anchorAlignment: "center" }), jsx("silkscreentext", { text: "LTE", ...pos(-5.2, -10), fontSize: 0.7, anchorAlignment: "center" }), jsx("silkscreentext", { text: "GNSS", pcbX: 6.2, pcbY: -8.4, fontSize: 0.7, anchorAlignment: "center" }), jsx("silkscreentext", { text: "WIFI", pcbX: 13.75, pcbY: 0.4, fontSize: 0.7, anchorAlignment: "center" }), jsx("silkscreentext", { text: "SOS", pcbX: 2.5, pcbY: 12.1, fontSize: 0.6, anchorAlignment: "center" })] }));
export { U5, index_circuit as default };