mohan-bee/rc-link-breakaway-panel

ISSUES.md

# tscircuit issues encountered

## Trace-width checks compare unrelated branches on a net

Responsible: `tscircuit/checks`, `checkSourceTracesMatchPcbTraceThickness`. Confirmed in installed 0.0.247 and published 0.0.256 source.

The function selects every PCB trace connected to the source trace's entire net, then reports its smallest width. A dedicated 1.5 mm ground bus between servo headers is therefore reported as 0.2 mm because an unrelated MCU ground branch is 0.2 mm. The original five servo-supply bus warnings likewise cited the separate 0.8 mm supply feed, even though all five header-to-header bus segments were already 1.5 mm.

The real supply/return feed weaknesses are now addressed: both dedicated feeds and buses are 1.5 mm, and the return feed runs on bottom through plated header holes. Five supply warnings disappear. Six ground-net warnings remain as checker false positives; no warning suppression is applied. `validation/servo-power-audit.json` proves a dedicated >=1.5 mm path from the supply/return connector to every servo header without relying on any 0.2 mm branch or small via, and records each warning's mismatched source trace. The path resistance calculation excludes the parallel ground planes, so it does not rely on a narrow thermal spoke or unspecified plane neck.

See the [top supply and header buses](./manufacturing/receiver-power-top.png) and [bottom dedicated return feed](./manufacturing/receiver-power-bottom.png). Copper pours are hidden in these diagnostic snapshots; production Gerbers retain them.

## PCB-only footprint modifiers reach the 3D model resolver

The transmitter passives used `0402_nosilkscreen` / `0603_nosilkscreen` PCB footprints. Core copied those strings into `cad_component.footprinter_string`, but the browser 3D renderer rejected them with `Invalid footprint function, got "undefined"`. PCB compilation succeeded, so a successful local build did not expose the published-viewer failure.

The project now supplies explicit standard-package GLB models from modelcdn for these passives. Both model URLs return valid GLB files. The physical footprint strings, copper and routing are preserved. `tools/check-built.mjs` rejects CAD records containing the PCB-only `_nosilkscreen` modifier. The platform boundary between core CAD metadata and the 3D footprint resolver still needs an upstream fix.

## Four-layer plated holes lose inner layers in native panels

Responsible: `tscircuit/core`, `PlatedHole.getAvailablePcbLayers()`.

The initial `<panel><board layers={4}>…</board></panel>` build emitted plated-hole `layers: ["top", "bottom"]`, while the same source built as a standalone board emitted all four layers. The method uses `this.root?._getBoard()` instead of the containing board. Physical connectivity analysis found opens at inner-layer connections to headers. Panel placement checks also treated components on another unit as outside the first board.

The released design avoids this path: it is a single four-layer root board with two isolated circuit groups and explicit routed slots. `tools/audit-panel.py` asserts all 54 plated holes and 268 vias span all four layers. It also verifies that original TX copper and RX signal copper are preserved (the RX servo power nets are intentionally upgraded). This is a design-level avoidance, not a platform fix.

## Polygon cutouts omitted in the generated 3D preview

Observed in `tsci build --site` with CLI 0.1.2332 / core 0.0.2152. The actual Circuit JSON and native Gerbers contain nine routed openings, independently verified in `validation/cam-audit.json`; the generated `dist/index/3d.png` shows an uncut rectangle. The exact downstream 3D package responsible has not been isolated.

Compare [routed snapshot](./panel-routed.png) against [native 3D preview](./dist/index/3d.png). Do not interpret that 3D preview as the fabrication outline.

## Partial schematic-placement check attempts routing without PCB ports

`tsci check schematic-placement index.circuit.tsx` fails in `getSimpleRouteJsonFromCircuitJson` while reading `connectedPort.x`. The full build succeeds and running `runAllSchematicChecks` on its output returns no findings. The completed-build checks are recorded by `tools/check-built.mjs`; the CLI failure is not treated as a passed check.