mohan-bee/infrared-battle-tag

ISSUES.md

# tscircuit issues found while building IR battle tag

Verified 2026-09-18 with Bun 1.3.14, tscircuit 0.0.2571, @tscircuit/cli 0.1.2095, @tscircuit/core 0.0.1933, @tscircuit/props 0.0.660, and @tscircuit/checks 0.0.199. These are local reports, not upstream issue submissions.

## P1 — Imported four-pad switch omits permanent internal connections

**Affected path:** `tsci import C381039 --jlcpcb --use-exact-footprint` → EasyEDA import / generated `TS_1102S_C_C_B.tsx`.

**Expected:** TS-1102S-C-C-B terminals 1–2 are permanently joined; terminals 3–4 are permanently joined. Pressing joins the two pairs. Preserve those connections in the generated component, and attach the schematic's second terminal to pin 3 rather than pin 2.

**Actual:** The generated `<pushbutton>` has four pin labels and four physical pads, but no `internallyConnectedPins`. The core primitive defaults to no internal pairs, so the schematic uses pins 1 and 2 as opposite switched terminals. Connecting pin 3 to GND does not draw the expected ground connection at the second schematic terminal.

**Electrical impact:** A design using pin 1 for VCC and pin 2 for GND would short the real supply permanently. The imported model instead treats these as separate nets. The minimal reproduction below reports **Errors: 0 / Warnings: 0** while listing pin 1 as VCC and pin 2 as GND. This is a device-model defect, not a demonstrated copper-router short; bitmap copper checks cannot discover missing internal device connections.

```sh
bunx tsci check netlist evidence/switch-pair-repro.circuit.tsx
bunx tsci build evidence/import-repro.circuit.tsx --routing-disabled --schematic-png
```

Reproduction: [switch-pair-repro.circuit.tsx](evidence/switch-pair-repro.circuit.tsx). **Do not fabricate the reproduction.** Output: [switch-pair-netlist.txt](evidence/switch-pair-netlist.txt). Original component: [original import](evidence/original-imports/TS_1102S_C_C_B.tsx).

![Imported schematic loses the grounded second terminal](evidence/images/switch-missing-terminal.png)

![Manufacturer circuit diagram shows the permanent terminal pairs](evidence/images/switch-datasheet-pairs.png)

Source: [XKB manufacturer drawing, distributed by LCSC](https://datasheet.lcsc.com/datasheet/pdf/349ea2b0800ca7ed2f4ff17b375109e4.pdf), circuit diagram and numbered top view.

**Local workaround applied:** `internallyConnectedPins={[["pin1", "pin2"], ["pin3", "pin4"]]}` in the imported switch. Actual SW1/SW2 connect pins 1–2 to the pulled-up GPIO and pins 3–4 to GND. No supply rail is wired directly across either switch.

## P2 — ATtiny1616 import drops multiplexed signal aliases, including UPDI

**Affected path:** `tsci import C614136 --jlcpcb` → `ATTINY1616_SN.tsx`.

**Actual:** Pins 8, 9, 16 and 19 become `pin8`, `pin9`, `pin16`, `pin19`; the rendered box has blank inner labels for these pins. Pin 16's UPDI function is missing. This obscures the programming interface and forces a manual datasheet audit. The physical pin numbers are preserved; an actual reversed pin assignment was not observed.

**Expected:** 8 = PB3/TOSC1, 9 = PB2/TOSC2, 16 = PA0/RESET/UPDI, 19 = PA3/EXTCLK for the **20-pin SOIC**. Do not reuse the differently numbered QFN pinout.

```sh
bunx tsci build evidence/import-repro.circuit.tsx --routing-disabled --schematic-png
```

![Unmodified imported MCU has blank labels on pins 8, 9, 16 and 19](evidence/images/mcu-missing-aliases.png)

![Microchip SOIC pinout](evidence/images/mcu-datasheet-pinout.png)

Source: [Microchip DS40001893B, page 15](https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/40001893B.pdf). Original component: [original import](evidence/original-imports/ATTINY1616_SN.tsx).

**Local workaround applied:** Restore those aliases and connect physical pin 16 to J2 pin 2. The game-reset button uses PB0; UPDI remains available.

## P2 — Imported transistor symbol has colliding pin labels and no reference text

**Affected path:** `tsci import MMBT2222A --jlcpcb` → C82460 / `MMBT2222ALT1G.tsx`.

**Actual:** The custom symbol is generated as a `<chip>`, has a very small 0.2 × 0.4 schematic body, and places B/C/E label text over the transistor drawing. It has no reference-designator text. The placement checker reports `SchematicBoxInnerLabelCollision`; its suggestion to enlarge `schWidth`/`schHeight` is not sufficient for the explicit custom paths and ports.

```sh
bunx tsci check schematic-placement evidence/import-repro.circuit.tsx
```

Output: [import-repro-check.txt](evidence/import-repro-check.txt). Original component: [original import](evidence/original-imports/MMBT2222ALT1G.tsx).

![Actual exported transistor crop showing overlapping labels and absent Q1](evidence/images/transistor-label-collision.png)

**Local workaround applied:** Use a transistor primitive with the imported custom NPN drawing and footprint; remove the redundant B/C/E display aliases from its custom ports; add an explicit Q1 text using the component name. Retain physical pin 1 = base, 2 = emitter, 3 = collector, with numeric trace selectors. [Onsemi pinout](https://www.onsemi.com/pdf/datasheet/mmbt2222lt1-d.pdf).

## P1 — KiCad ZIP silently omits the child schematic

**Affected path:** CLI 0.1.2095 `tsci export ... -f kicad_zip`, with a `<schematicsheet>` in the design. Converter version: `circuit-json-to-kicad` 0.0.212.

```sh
bunx tsci export dist/index/circuit.json -f kicad_zip -o infrared-battle-tag.kicad.zip
unzip -l dist/index/infrared-battle-tag.kicad.zip
unzip -p dist/index/infrared-battle-tag.kicad.zip circuit.kicad_sch
```

**Actual:** Export exits successfully. The root contains `(property "Sheetfile" "main.kicad_sch")`, but `main.kicad_sch` is absent from the ZIP. The root contains no circuit symbols; all 24 components live in the missing child. Opening the archive as a complete KiCad project therefore cannot recover the actual schematic.

**Expected:** Include every file returned by the converter's `getOutputFiles({schematicFilename: ...})`, not only the root returned by `getOutputString()`.

**Confirmed cause:** The CLI's `kicad_zip` branch writes `schConverter.getOutputString()` once. Its bundled converter explicitly provides `getOutputFiles()` for hierarchical designs. The standalone `kicad_sch` branch also writes only the root; avoid using that as a complete schematic export for this design.

Evidence: [original broken archive](evidence/broken-cli-kicad.zip), [archive inventory](evidence/broken-zip-inventory.txt), [root schematic text](evidence/broken-root.kicad_sch.txt).

The following crop is the actual tscircuit sheet content that the missing child should contain:

![Circuit content absent from the original KiCad ZIP](evidence/images/missing-kicad-child-content.png)

**Local workaround applied:** [repair-kicad-export.ts](evidence/repair-kicad-export.ts) replaces the schematic hierarchy in the exported archive with **all** converter outputs. It verifies every referenced child exists and checks the principal component references. The corrected deliverable is [infrared-battle-tag.kicad.zip](infrared-battle-tag.kicad.zip); [repair log](evidence/kicad-repair.txt). The raw archive inside `dist/index/` remains the CLI's incomplete output for reproducibility. KiCad desktop rendering was not available here, so the corrected archive is structurally verified, not independently opened in KiCad.

## Assembly-export limitation

The Gerber export also emits `missing_pin1_location` warnings for its generated pick-and-place CSV. This is an unverified rotation warning, not proof of a wrong rotation. [Export log](evidence/export-gerbers.txt). Review all assembly rotations and unspecified generic passive/indicator part selections before submitting an automated assembly job. Copper/drill files and the short-check results are separate from those assembly metadata warnings.

## Final board verification

The defects above have local workarounds in the actual design or corrected deliverable. No node_modules patches, disabled placement rules, or ignored build errors are needed.

- [Netlist](evidence/netlist.txt): 0 errors, 0 warnings.
- [Schematic placement](evidence/schematic-placement.txt): no findings (the CLI emits an empty result on success).
- [PCB placement](evidence/placement.txt): no placement issues; placement DRC 0 errors, 0 warnings.
- [Routed build](evidence/build-routed.txt): successful.
- [Independent physical-pin audit](evidence/connectivity-audit.txt): 18 intended nets / 63 connected physical pins, including the switch's permanent connections; no unintended net merges.
- [Gerber-based short check](evidence/shorts-gerber.txt) and [PCB-based short check](evidence/shorts-pcb.txt): see saved final results. No copper short was found in the tested board.

These checks validate the modeled circuit and generated copper. They do not substitute for physical bring-up or validate game firmware. No firmware has been supplied in this hardware task.