mohan-bee/fitness-band

validation/main-build.log

$ tsci build index.circuit.tsx --pcb-png --svgs --autorouter-timeout 60s
Building 1 file(s)...
Building index.circuit.tsx...
Generating circuit JSON...
Each child in a list should have a unique "key" prop.

Check the render method of `MainBoard`. It was passed a child from FlexConnections. See https://react.dev/link/warning-keys for more information.
Each child in a list should have a unique "key" prop.

Check the render method of `MainBoard`. See https://react.dev/link/warning-keys for more information.
Saved autorouting paths to .tscircuit/autorouting-artifacts/index-circuit-tsx-2e2764dae4/subcircuit_source_group_0-phase-default-order-0.pcb-trace-paths.json (import this JSON into <autoroutingphase pcbTracePaths={...} />).
Circuit JSON written to dist/index/circuit.json
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
Port VBUS on U1 is missing a trace
J_SWD has no pin with requires_power=true
J_SWD has no pin with requires_ground=true
All pins on J_SWD are underspecified (no pinAttributes set)
U2 has no pin with requires_power=true
U2 has no pin with requires_ground=true
All pins on U2 are underspecified (no pinAttributes set)
J_BAT has no pin with requires_power=true
J_BAT has no pin with requires_ground=true
All pins on J_BAT are underspecified (no pinAttributes set)
J_CHG has no pin with requires_power=true
J_CHG has no pin with requires_ground=true
All pins on J_CHG are underspecified (no pinAttributes set)
U6 has no pin with requires_power=true
J_FLEX has no pin with requires_power=true
J_FLEX has no pin with requires_ground=true
All pins on J_FLEX are underspecified (no pinAttributes set)
No <schematicsheet> was found. Add a <schematicsheet> to define the schematic drawing area.
J_SWD has no courtyard
J_BAT has no courtyard
J_CHG has no courtyard
J_FLEX has no courtyard
.U2 > .SDA to net.SDA has a 5.36 mm segment on top at 258.17°, 11.83° from the nearest allowed direction (270°). Prefer a multiple of 45° for segments longer than 5 mm (tolerance 4°).
<resistor#340 name=".R3" /> footprint "0402" does not match supplier footprint jlcpcb:C25900 (copper IoU 0.7741).
<capacitor#170 name=".C2" /> footprint "0402" does not match supplier footprint jlcpcb:C1525 (copper IoU 0.7249).
L1 may not have availability from jlcpcb (C501946).
<capacitor#266 name=".C10" /> footprint "0402" does not match supplier footprint jlcpcb:C1525 (copper IoU 0.7249).
<resistor#327 name=".R2" /> footprint "0402" does not match supplier footprint jlcpcb:C25744 (copper IoU 0.7741).
<resistor#366 name=".R5" /> footprint "0402" does not match supplier footprint jlcpcb:C25900 (copper IoU 0.7741).
<resistor#314 name=".R1" /> footprint "0402" does not match supplier footprint jlcpcb:C25744 (copper IoU 0.7741).
<capacitor#278 name=".C11" /> footprint "0402" does not match supplier footprint jlcpcb:C1525 (copper IoU 0.7249).
<capacitor#254 name=".C9" /> footprint "0402" does not match supplier footprint jlcpcb:C1525 (copper IoU 0.7249).
<resistor#353 name=".R4" /> footprint "0402" does not match supplier footprint jlcpcb:C25900 (copper IoU 0.7741).
U1 may not have availability from jlcpcb (C5118826).
Generating preview images...
[index] Generating PCB SVG...
[index] Written pcb.svg
[index] Generating PCB PNG...
[index] Written pcb.png
[index] Generating schematic SVG...
[index] Written schematic.svg

Build complete
  Circuits  1 passed
  Options   pcb-png, svgs, autorouter-timeout
  Output    dist

✓ Done
Build exiting with code 0: build finished successfully