jettos/powercore16-revc-complete-board-model

This code defines the hardware layout for a power distribution and control circuit featuring high-current power inputs, multiple output switches with programmable fuses, MCU-based control, input connectors, and communication interfaces, all represented with specific component footprints and connectivity zones.

Version: 0.4.8
License: unset
Stars: 0

src/components/TestPoints.tsx

export function TestPoints() {
  const nets = ["VBAT_IN", "VBAT_PROTECTED", "PWR_GND", "5V_INTERNAL", "3V3_INTERNAL", "5V_SENSOR_A_PROTECTED", "5V_SENSOR_B_PROTECTED", "CAN_H", "CAN_L", "TEMP_SENSE", "VBAT_SENSE"]
  return <>
    {nets.map((net, i) => <>
      <testpoint name={`TP_${net}`} pcbX={-104 + i * 12} pcbY={-6} />
      <silkscreentext text={`TP ${net}`} pcbX={-104 + i * 12} pcbY={-12} fontSize="0.55mm" />
    </>)}
    <chip name="U_BOARD_TEMP_SENSOR" footprint="soic8_p1.27mm" pcbX={56} pcbY={-10} />
    <silkscreentext text="OUT current sense group test points at each U_OUTx" pcbX={-8} pcbY={4} fontSize="0.75mm" />
    <silkscreentext text="Input test points at IN1-IN16 filter outputs" pcbX={-8} pcbY={-4} fontSize="0.75mm" />
  </>
}