jettos/powercore16-revc-complete-board-model

This code defines the hardware layout for a power distribution and control circuit featuring high-current power inputs, multiple output switches with programmable fuses, MCU-based control, input connectors, and communication interfaces, all represented with specific component footprints and connectivity zones.

Version: 0.4.8
License: unset
Stars: 0

src/components/PowerProtection.tsx

export function PowerProtection() {
  return <>
    <chip name="U_REVERSE_CONTROLLER" footprint="soic8_p1.27mm" pcbX={-88} pcbY={12} />
    <chip name="Q_REVPROT_A" footprint="soic8_p1.27mm" pcbX={-78} pcbY={20} />
    <chip name="Q_REVPROT_B" footprint="soic8_p1.27mm" pcbX={-68} pcbY={20} />
    <diode name="D_LOAD_DUMP_TVS" footprint="soic8_p1.27mm" pcbX={-84} pcbY={-9} />
    <capacitor name="C_BULK_INPUT" capacitance="470uF" footprint="soic8_p1.27mm" pcbX={-72} pcbY={-9} />
    <resistor name="R_GATE_SUPPORT" resistance="100" footprint="0603" pcbX={-92} pcbY={21} />
    <chip name="FB_SURGE_RETURN" footprint="soic8_p1.27mm" pcbX={-84} pcbY={-28} />
    <silkscreentext text="LOAD DUMP / TVS REQUIRES VALIDATION" pcbX={-64} pcbY={2} fontSize="0.95mm" />
    <silkscreentext text="REVERSE PROTECTION SOA REQUIRES VALIDATION" pcbX={-58} pcbY={34} fontSize="0.95mm" />
    <silkscreentext text="VBAT_IN -> reverse MOSFET bank -> VBAT_PROTECTED" pcbX={-57} pcbY={26} fontSize="0.85mm" />
  </>
}