jettos/powercore16-revc-complete-board-model

This code defines the hardware layout for a power distribution and control circuit featuring high-current power inputs, multiple output switches with programmable fuses, MCU-based control, input connectors, and communication interfaces, all represented with specific component footprints and connectivity zones.

Version: 0.4.8
License: unset
Stars: 0

src/components/MainPowerInput.tsx

export function MainPowerInput() {
  return <>
    <chip name="J_BAT_POS" footprint="soic8_p1.27mm" pcbX={-112} pcbY={18} />
    <chip name="J_BAT_GND" footprint="soic8_p1.27mm" pcbX={-112} pcbY={-18} />
    <resistor name="R_VBAT_SENSE_HI" resistance="100k" footprint="0603" pcbX={-100} pcbY={5} />
    <resistor name="R_VBAT_SENSE_LO" resistance="10k" footprint="0603" pcbX={-94} pcbY={5} />
    <testpoint name="TP_VBAT_IN" pcbX={-104} pcbY={31} />
    <testpoint name="TP_VBAT_PROTECTED" pcbX={-68} pcbY={31} />
    <silkscreentext text="J_BAT_POS M6/M8 STUD - VBAT_IN" pcbX={-98} pcbY={28} fontSize="1.35mm" />
    <silkscreentext text="J_BAT_GND M6/M8 STUD - PWR_GND / surge return" pcbX={-92} pcbY={-30} fontSize="1.15mm" />
    <silkscreentext text="EXTERNAL UPSTREAM FUSE REQUIRED" pcbX={-82} pcbY={-38} fontSize="1mm" />
    <silkscreentext text="VBAT_SENSE divider to MCU ADC" pcbX={-86} pcbY={10} fontSize="0.8mm" />
  </>
}