jettos/powercore16-revc-complete-board-model

This code defines the hardware layout for a power distribution and control circuit featuring high-current power inputs, multiple output switches with programmable fuses, MCU-based control, input connectors, and communication interfaces, all represented with specific component footprints and connectivity zones.

Version: 0.4.8
License: unset
Stars: 0

src/components/DebugService.tsx

export function DebugService() {
  return <>
    <pinheader name="J_DEBUG" pinCount={6} footprint="soic8_p1.27mm" pcbX={44} pcbY={24} />
    <silkscreentext text="J_DEBUG internal only: SWDIO SWCLK RESET BOOT 3V3_INTERNAL LOGIC_GND" pcbX={44} pcbY={35} fontSize="0.85mm" />
    <silkscreentext text="3V3_INTERNAL allowed only here, not customer connectors" pcbX={44} pcbY={40} fontSize="0.75mm" />
    <silkscreentext text="RESET BOOT_SERVICE SWD/JTAG placeholder pins" pcbX={44} pcbY={19} fontSize="0.75mm" />
  </>
}