imrishabh18/rp2040-motor-controller

reports/verification.md

# PCB verification — 2026-09-05

**The final rebuild passes DRC, `tsci check`, the Gerber shorts check, and all seven tests.**

| Check | Final result |
|---|---|
| `bun run verify` | Pass, exit code 0 |
| TypeScript | Pass |
| Embedded circuit / PCB DRC errors | 0 |
| Independently rerun `runAllRoutingChecks` errors | 0 |
| `tsci check dist/index/circuit.json` | Errors: 0 |
| Gerber shorts, all copper layers | No shorts detected |
| Tests | 7 pass, 0 fail; 487 assertions |
| Common ground | Both GND declarations and 18 required ground pins joined |
| Current-sense connections | Both channels connected through their respective shunts |
| Motor outputs | All four reach their terminals and remain separate |

## Final changes

- `BOARD_GND_JOIN` explicitly connects the board ground and its pours to the MCU/driver/USB ground network.
- `ISEN_B_ESCAPE` defines the current-sense layer transition at (4.65, -12.75) mm, with a 0.30 mm drill and 0.45 mm pad. The clearance to DRIVER.BOUT2 is approximately **0.186 mm**, exceeding the unchanged 0.10 mm DRC requirement.
- The fault network routes first, then A−, then the remaining motor outputs. The motor-output phase uses a 0.20 mm trace-to-pad routing margin. Global DRC limits and the power-trace test thresholds were not relaxed.
- The source keeps the original component positions, 50 × 49 mm board outline, two layers, connectors, and mounting holes. Experimental driver/capacitor moves and the extra motor escape vias were reverted.
- The ISEN_B test follows the routed connection name when tscircuit assigns the trace's canonical source ID to the explicit via's connectivity record.
- `bun run verify` also guards against the CLI returning exit code zero while printing errors.

## Warnings and scope

`tsci check` still reports **139 warnings**, including supplier-footprint lookup failures, trace-length warnings, missing courtyards, pin metadata, and schematic styling. These remain visible in the logs; zero errors does not mean zero warnings. The tests include stock-audit parser tests, not a new stock audit.

This report applies to the rebuilt design files. It does not change the already fabricated PCB. The source and verified build are prepared for publication with `tsci push`.

## Reproduce

```sh
bun install --frozen-lockfile
bun run verify
bun run render:schematic
bun scripts/render-pcb.ts
```

Circuit JSON SHA-256: `a66e28d965deeb6d88ce9c66c84a21cf1fd4e40811070604ce5bf5b6c92f2578`

Toolchain:

- `tscircuit`: `0.0.2463`
- `@tscircuit/core`: `0.0.1844`
- `@tscircuit/cli`: `0.1.2021`
- `@tscircuit/common`: `0.0.48`
- `@tscircuit/capacity-autorouter`: `0.0.866`
- `@tscircuit/checks`: `0.0.183`
- `circuit-json`: `0.0.485`
- `circuit-to-svg`: `0.0.413`

The customized `@tscircuit/common@0.0.48` is retained to preserve the board's RP2040 footprint, placement, and decoupling corrections. The compiler, core, CLI, router, and checks are the upgraded versions recorded above.

`reports/validation.json` records the exact artifact hash and DRC results. `reports/verify.log` contains the final end-to-end run; `reports/tsci-check.log` and `reports/shorts.log` record the CLI checks. The ZIP includes the source, lockfile, generated Circuit JSON, and updated top/bottom PCB previews.