imrishabh18/rp2040-motor-controller

reports/original-v1.0.13-README.md

# RP2040 Motor Controller

A tscircuit board combining the reusable `Microcontroller_RP2040` from
`@tscircuit/common` with a TI DRV8847 dual H-bridge configured for one bipolar
stepper motor.

## Features

- RP2040, USB-C, flash, crystal, 3.3 V regulation, boot/run controls, and SWD
  test points from `@tscircuit/common`
- one four-wire bipolar stepper motor controlled by GPIO18-GPIO21
- DRV8847 sleep control on GPIO22 and active-low fault feedback on GPIO23
- dedicated USB-C motor-power input with a CH224K PD sink requesting 9 V
- 1 A current regulation per coil using 0.15 ohm sense resistors
- solder-mask-covered GND copper pours on the top and bottom layers
- one four-position screw terminal labeled A+, A-, B+, and B-
- four 3.2 mm mounting holes

The RP2040 control circuitry and motor driver have separate USB-C ports. The
motor port negotiates a 9 V USB PD contract when the source supports it; its
VBUS drives the DRV8847 motor rail. The grounds are shared. The 9 V request is
within the DRV8847's 2.7 V to 18 V operating range.

## Development

```sh
bun install
bun run typecheck
bun test
bun run build
bun run snapshot:update
```

The DRV8847 support network includes local 10 uF and 100 nF VM decoupling and
separate 0.15 ohm current-sense resistors for the two coils. The selected
DRV8847PWPR is JLCPCB/LCSC part C544361. The four-position 5.08 mm stepper
terminal is WJ500V-5.08-04P-14-00A, JLCPCB/LCSC part C42377749.

The motor-power port uses CH224K JLCPCB/LCSC part C970725 and USB-C receptacle
C2765186. A 6.8 kohm CFG1 resistor selects the 9 V request. The CH224K VDD and
VBUS-sense pins use 1 kohm and 10 kohm series resistors respectively, with 1 uF
local VDD decoupling and 10 uF on the motor VBUS rail.

## Power-trace routing

The PCB is 50 x 49 mm with two copper layers and 0.3 mm via holes / 0.45 mm
via pads. The board and reusable RP2040 subcircuit both explicitly use 10x
autorouter effort. The lower sense resistors are spaced away from the driver
outputs to leave a wider routing channel. Crystal signal traces retain their
zero-via constraints.

The board uses capacity autorouter Pipeline 7. Power-trace expansion is part of
that pipeline, so the circuit does not import or run a separate post-routing
solver. Connections whose requested width is materially larger than the board's
ordinary routing width are expanded automatically after the multigraph route.

After routing, the board generates top- and bottom-layer pours tied to one
explicit board-level `GND` net. Both use 0.2 mm pad/trace clearance and remain
0.3 mm inside the board edge. The board regression requires B-Rep pour islands
on both layers to share the same ground net and remain covered by solder mask.

The board test independently reruns `@tscircuit/checks` routing validation on
the completed Circuit JSON and requires zero routing or circuit errors. It also
uses shape-aware pad geometry to reject any routed via inside an SMT pad.

The pad-clearance target is intentionally best-effort: dense package escapes
may keep the board's legal 0.1 mm minimum when half-width spacing cannot fit.
The regression separately budgets the remaining 0.15 mm preferred-clearance
misses while still requiring the hard DRC suite to be completely clean.

Also run `bun run check:shorts` before exporting fabrication files. This checks
the Gerber-rendered copper, including pours and widened trace endpoints; these
can reveal shorts that the normal routing checks miss. When changing router
version or effort, invalidate the local routing cache before validation: the
current cache key does not distinguish those settings.

The current 50 x 49 mm build passes the embedded circuit checks, independently
rerun routing DRC, and the all-layer Gerber short check. It is not yet
fabrication-approved: the motor-output width regression still fails on A-.
Its longest run below 0.85 mm is 7.28 mm (the test permits 5 mm), and its
length-weighted average width is 0.781 mm (the test requires more than 0.8 mm).
The test thresholds have not been relaxed. A four-layer trial was not retained:
it still had clearance errors and generated partial-span vias instead of a
standard through-via-only layout.

## JLCPCB stock audit

After building the current circuit, run `bun scripts/audit-jlcpcb-stock.mjs` to
check public JLCPCB inventory and generate `reports/jlcpcb-stock-audit.csv` and
`reports/jlcpcb-stock-audit.json`. The JSON includes the input Circuit JSON hash,
per-part timestamps, displayed stock, and available order quantities. The command
fails if a populated component lacks a code or a part is unverified/unavailable
for even one board. Bare copper test pads are excluded; they are not purchased parts.

The 2026-08-26 audit found codes for all 58 populated components (33 unique parts).
32 unique parts had positive available order quantities. J1, C42377749, showed
150 units but zero available stocked-order quantity; its product page offered
preorder with a 28-piece minimum. Confirm procurement or validate a replacement
before ordering assembly. No parts have been purchased or reserved.

These reports are stock audits, not fabrication BOM/PnP files or design approval.
Availability can change; check the actual board quantity, assembly attrition,
minimums, and checkout availability. The existing
`dist/rp2040-motor-controller-gerbers.zip` is outdated and must not be submitted.
The electrical and mechanical issues from the fabrication review remain open.