imrishabh18/rp2040-motor-controller

engineering/pd-power-good.md

# CH224K power-good readback

The CH224K PG pin continues to drive the BSS84 motor-sleep interlock. A new high-impedance sensing input also lets the RP2040 read its status on **GPIO7 (physical pin 9)**. The INA226 remains the source of numeric PD voltage measurements.

U_PD_PG is a TI SN74LVC1G97DRLR, powered by the DATA USB domain's 3.3 V rail. It accepts the independent CH224K domain on its inputs, including when its own supply is off. Schmitt inputs tolerate the slow supply and 100 kΩ PG pull-up transitions. Its Ioff specification provides partial-power-down protection; this is not galvanic isolation.

The physical configuration follows TI's function table:

| Buffer pin | Connection |
| --- | --- |
| 1 / In1 | CH224K VDD; 47 kΩ discharge resistor R_PD_VDD_PD to GND |
| 2 / GND | Common GND |
| 3 / In0 | GND (selects the required logic function) |
| 4 / Y | RP2040 GPIO7 / PD_GOOD; 10 kΩ R_PD_GOOD_PD to GND |
| 5 / VCC | MCU 3.3 V; 100 nF C_PD_PG bypass |
| 6 / In2 | Existing active-low CH224K PG node |

With In0 low, Y = In1 AND NOT In2. The firmware-facing signal is **active high**, although CH224K PG itself is active low.

| DATA / MCU supply | CH224K supply | Raw PG | GPIO7 |
| --- | --- | --- | --- |
| On | On | Low / asserted | High / power good |
| On | On | High / deasserted | Low / not good |
| On | Off | Unpowered | Low after the PD rail discharges |
| Off | On or off | Any | No valid firmware reading; buffer is unpowered |

R_PD_VDD_PD prevents the unpowered PD domain from floating and falsely asserting good. Allow rail discharge and logic settling after plugging/unplugging; this is a status input, not a precision undervoltage supervisor. R_PD_GOOD_PD holds the output near GND with the buffer unpowered. Worst-case 10 µA output leakage across 10 kΩ is 0.1 V. With MCU power on, the PG input's 5 µA maximum leakage gives at most 0.5 V drop across the existing 100 kΩ pull-up; a 3.24 V PD rail still gives at least 2.74 V at a deasserted PG input.

All four added components are populated on top. The optional bottom encoder remains doNotPlace. The PG pull-up remains on CH224K VDD; the buffer does not replace or bypass Q_PD_ENABLE. GPIO22 still requests motor enable through that hardware interlock.

Firmware must configure GPIO7 as an **input with internal pulls disabled**, read high as good, and also confirm the requested voltage using INA226 at I²C address 0x40 before raising GPIO22. Keep GPIO22 low during negotiation and voltage changes. No application firmware or powered prototype test is included in this design change.

Reference: [TI SN74LVC1G97 datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc1g97.pdf), pin configuration, function table, input leakage, Schmitt thresholds and Ioff specifications. The exact JLCPCB footprint is C2682094.

The PCB retains all existing component positions and 287 of the 288 prior trace geometries. One local 3.3 V I/O bypass escape (`top_assembly_215`) is rerouted to allow GPIO7 fanout; twelve new PG-related branches are added. The schematic uses automatic groups for PG readback and PD supply discharge, without component or group X/Y overrides.