imrishabh18/pedometer

docs/interfaces.md

# Interface and physical pin cross-reference

All addresses below are **7-bit**. Start at 100 kHz with 10 kΩ main-bus pull-ups to 2.5 V; measure rise time with the actual cable. The OLED board provides its own 3.3 V pull-ups. Faster operation requires checking bus capacitance and sink-current limits.

| Device | I2C address | SDA physical pin/ball | SCL physical pin/ball | Other connections |
|---|---|---|---|---|
| CC2340R52E0RGER | Controller | Pin 3, DIO8 | Pin 19, DIO6 | Main 2.5 V |
| BMA400 | 0x14 | 2, SDI | 12, SCK | CSB pin 10 to 2.5 V; SDO pin 1 to ground |
| BQ25150 | 0x6B | E2 | E3 | VIO 2.5 V; LP DIO11; INT DIO13 |
| BQ27427 | 0x55 | A2 | A3 | GPOUT A1 → DIO21 |
| SSD1306 / Adafruit 4440 | 0x3C | J3.3 | J3.4 | Switched 3.3 V through PCA9306 |

| Function | CC2340R5 DIO | U1 QFN pin |
|---|---:|---:|
| I2C SCL | 6 | 19 |
| I2C SDA | 8 | 3 |
| Accelerometer INT1 | 12 | 5 |
| Gauge GPOUT | 21 | 10 |
| PMIC INT | 13 | 6 |
| Button / PMIC PG | 24 | 12 |
| PMIC LP | 11 | 4 |
| Display isolation | 20 | 9 |
| SWDIO | 16 | 7 |
| SWCLK | 17 | 8 |
| LF crystal P / N | 3 / 4 | 14 / 15 |
| Reset | — | 13 |


## I2C versus SPI

| Part | I2C implementation here | SPI alternative | PCB consequences |
|---|---|---|---|
| BMA400 | CSB high, SDO low → 0x14 | SCK 12, SDI/MOSI 2, SDO/MISO 1, CSB 10; 3- or 4-wire supported | Cut/replace the address and mode straps, provide CS and MISO and remap MCU bus pins; not a firmware-only conversion |
| Adafruit 128×32 OLED | STEMMA QT four-wire I2C, 0x3C | The breakout design can be reconfigured for SPI using its documented jumpers and extra header signals | Current J3 has no CS, D/C, reset or SPI wiring; select and wire a compatible display variant before changing |
| BQ25150 / BQ27427 | Shared I2C | No SPI interface | Remain on I2C |

The selected QFN24 exposes SPI SCLK on DIO8 or DIO24, MOSI on DIO12 or DIO13, MISO on DIO11/12/13/20 and chip select options including DIO11/DIO6. These conflict with functions assigned in this design. Do not assume an arbitrary GPIO mapping; select a valid combination in TI SysConfig and revise the net map. For a low-rate step counter and occasional 512-byte screen refresh, I2C saves pins and is sufficient.

Sources: [TI CC2340R5 pin-function table](https://www.ti.com/lit/ds/symlink/cc2340r5.pdf), [Bosch BMA400 interface specification](https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bma400-ds000.pdf), [Adafruit wiring guide](https://learn.adafruit.com/monochrome-oled-breakouts), [Adafruit schematic files](https://github.com/adafruit/Adafruit-128x32-I2C-OLED-Breakout-PCB).

## Connector numbering

| Reference | Pins in order | Notes |
|---|---|---|
| J1 | 1 PACK+, 2 GND, 3 NTC | JST BM03B-SRSS-TB(LF)(SN); retention tabs 4/5 ground |
| J2 | 8 B12/GND, 9 B9/VBUS, 10 A5/CC1, 11 B5/CC2, 12 A9/VBUS, 13 A12/GND | SHOU HAN TYPE-C 6P / C456012; footprint pins 1–4 are separately routed grounded shell tabs |
| J3 | 1 GND, 2 OLED_3V3, 3 SDA, 4 SCL | JST BM04B-SRSS-TB; shell pads 5/6 ground; verify cable order at both ends |
| J4 | 1 VTREF 2.5 V, 2 SWDIO, 3 SWCLK, 4 GND, 5 RESET_N | JST BM05B-SRSS-TB(LF)(SN); retention tabs 6/7 ground; VTREF senses target supply |

J1, J3 and J4 have 1.0 mm pitch and top-entry mating. J2 is a side-entry USB-C receptacle at the top board edge. The signal pin numbers follow the manufacturer's pin-1 mark; imported retention-tab numbers are additional PCB pads, not cable positions. Cable colors do not establish polarity.

| Cable | Mating housing | Assembly |
|---|---|---|
| J1 battery | SHR-03V-S | PACK+, GND and a cell-mounted 10 kΩ NTC; verify the pack harness against the pinout above |
| J2 charging | Standard USB-C cable | 5 V charging only; supports either plug orientation |
| J3 OLED | SHR-04V-S | GND, switched 3.3 V, SDA and SCL |
| J4 programming | SHR-05V-S | Adapter cable to a 2.5 V-compatible SWD debugger |

These housings use SSH-003T-P0.2-H contacts with the wire sizes specified by JST, or can be purchased as suitable precrimped cable assemblies. J4 uses the custom five-wire pinout above and requires an adapter to the debugger's own connector. Connect VTREF to the debugger's target-voltage sense input; it is not a power input. J2 is a 5 V USB-C sink. R12 and R13 are separate 5.1 kΩ, 1% CC pull-downs; D1 clamps VBUS transients. Both VBUS contacts connect to VIN5 and the BQ25150 input. There is no USB data interface, USB PD controller or connection to SWD. Keep the BQ25150 default 100 mA input limit; firmware sets nominal 20 mA charging. The passive CC network does not detect higher advertised current. The connector shell overhangs the PCB edge (allow approximately 2 mm for the shell, plus plug clearance); allow plug and enclosure clearance. [JST SH connector and mating-part specification](https://www.jst-mfg.com/product/pdf/eng/eSH.pdf).

## BGA import numbering

U2 imported pin numbers run A1,A2,A3,A4,B1…E4, one-based. Thus 1=IN, 2=PMID, 3=BAT, 4=GND, 5=PG, 6=PMID, 7=BAT, 8=TS, 9=MR, 10=CE, 11=IMAX, 12=ADCIN, 13=VDD, 14=INT, 15=LP, 16=LSLDO, 17=VIO, 18=SDA, 19=SCL, 20=VINLS.

U3 imported numbers run A1,B1,C1,A2,B2,C2,A3,B3,C3. Thus 1=GPOUT, 2=BIN, 3=VSS, 4=SDA, 5=VSS, 6=SRX, 7=SCL, 8=VDD, 9=BAT. Use ball labels when reviewing against TI drawings; imported rotation is not the same as the page orientation in the datasheet.


## USB-C source references

Connector pin names and geometry were checked against the [SHOU HAN drawing](https://datasheet.lcsc.com/datasheet/pdf/68548ae186bce8dcee36d39654e737cb.pdf?productCode=C456012). Library pin numbers 8–13 follow B12, B9, A5, B5, A9, A12 respectively. The four shared EH mounting pads were assigned independent shell pin numbers 1–4 so each physical tab is routed to ground. D1 uses [onsemi ESD5Z5.0T1G](https://www.onsemi.com/download/data-sheet/pdf/esd5z2.5t1-d.pdf), pin 1 cathode to VBUS and pin 2 anode to GND. This adds transient protection; it is not a USB PD or sustained-overvoltage power controller.