imrishabh18/pedometer

docs/fabrication-review.md

# Bare-chip Rev B fabrication review

**CAD checks pass. The package is ready for factory CAM review; ordering awaits process and RF-stackup acceptance.**

BGA via-in-pad is intentionally allowed. No charger replacement is required. The board exposes all programming signals on J4, but physical flashing and a complete TI target firmware application have not been tested.

| Check | Result |
|---|---|
| Board | 40 × 38 × 1 mm, four layers |
| DRC / tsci check | 0 errors, 0 warnings |
| Routed copper | 169 traces; 163 unique through-vias |
| Completeness | 0 unconnected ports, missing source traces or discontinuities |
| Programming | Five J4 connections pass routed continuity |
| PCB BOM | All 62 components have exact MPN/JLC codes |
| Export | Gerber exporter 0.0.104, unpatched; drill and BGA aperture audits pass |

## Findings

### PAD-01 — JLCPCB rejected passive footprints (resolved)

Replaced all 12 rejected references and four additional passives sharing the custom footprint function with exact JLCPCB/EasyEDA imports. All 32 pad shapes, dimensions, pitches and pin assignments match the untouched imports; copper, mask and paste are verified in the exported Gerbers. Electrical values, part numbers and netlist are unchanged.

### CAD-01 — Fully routed board and programming connector (resolved)

Fresh placement/routing checks, source-trace completeness, port connectivity and trace continuity all pass. All five J4 signals reach the MCU; reset bias is verified. SWCLK is routed in a dedicated top-only autorouting phase.

### FAB-01 — Physical drill spans and duplicate hits (resolved)

Unpatched Gerber exporter 0.0.104 emits 163 unique through-vias, four plated USB-C slots and two NPTH holes. No blind/buried or duplicate drill hits.

### FAB-02 — Copper and drill clearances (resolved)

Minimum pad-to-trace 0.114991 mm; trace-to-trace 0.114874 mm. Minimum drill-to-pad 0.209796 mm; drill-to-trace 0.212264 mm. No drill clearance violation below 0.20 mm; antenna keepout/pour intersection is zero.

### ASM-01 — BGA via-in-pad policy (resolved)

BGA via-in-pad is permitted. The tscircuit FanoutSolver validates seven interior escapes across U2/U3. Current drill/land overlap counts by component: {'U2': 4, 'U1': 1}. No manual via JSX elements are present.

### BOM-01 — PCB passive procurement (resolved)

All 62 PCB components have exact MPNs and JLCPCB codes. Stock was not revalidated for this revision. External battery, NTC, display and cable sourcing are separate.

### DOC-01 — Printable fabrication silkscreen (resolved)

Dense top references are retained in the assembly drawing. Fabrication uses four underside labels at 1.7 mm height and 0.153 mm stroke; copper and drill positions are preserved.

### ASM-02 — Filled/capped vias, BGA mask, stencil and panel process (open)

Approve resin-filled, planarized, copper-capped vias for all 163 plated vias (5 total drill/land overlaps). U2's 0.30 mm via annuli with 0.23 mm mask openings leave 0.035 mm radial overlap, below TI's illustrated 0.05 mm SMD overlap; explicit process acceptance is needed. Other BGA openings retain at least 0.119796 mm mask bridge. Approve the common/stepped stencil, ENIG and handling panel.

### RF-01 — RF impedance and stackup confirmation (open)

Factory CAM must confirm a four-layer, 1.0 mm stackup compatible with the routed 0.20 mm top RF feed, its coplanar spacing and In1_Cu ground reference at 50 ohms. Return geometry changes for rerouting. Antenna tuning, oscillator calibration and range testing follow on prototypes.

## Deliverable and verification limits

The CAM ZIP in `../fabrication/` contains the Gerbers, PCB-only BOM, CPL, assembly drawing, five schematic sheets, programming instructions, audit reports and hashes. CPL coordinates use the Gerbers’ board-center origin. Apply the included assembly requirements; this is not an approved order.

`check:fabrication` remains nonzero for ASM-02 and RF-01. Neither is a DRC or tsci-check error. Factory acceptance must resolve them before tooling. The external battery/NTC must be selected and its charger/gauge settings verified before cell use; physical RF, charging, runtime and firmware validation remain prototype work.

Circuit SHA-256: `384dff968fe32973bb6b1736216a0d754ce44283f269d087da7546204ef430cd`. Manufacturing SHA-256: `b59631c17cfc05992d3e8f93d93082f429d3cae881ba66667ec9f0b55b1f256d`.

Sources: [TI CC2340R5](https://www.ti.com/lit/ds/symlink/cc2340r5.pdf), [TI BQ25150 land/stencil drawings](https://www.ti.com/lit/ds/symlink/bq25150.pdf), [TI BQ27427](https://www.ti.com/lit/ds/symlink/bq27427.pdf), [JLCPCB capabilities](https://jlcpcb.com/capabilities/pcb-capabilities).