hrithik18k/open-ring-flex

docs/SCHEMATIC_LAYOUT.md

# Sectioned Open Ring schematic

Version 1.0.3 organizes the existing circuit into five native schematic sheets and 14 functional sections.

| Sheet | Sections |
| --- | --- |
| 01 Power and charging | Inductive input and rectifier; battery charger and system supply; input and haptic voltage monitors |
| 02 Bluetooth and RF | BLE processor and clock; SPI flash; 2.4 GHz matching network and antenna |
| 03 Touch and wear sensing | SAM L10 touch controller and supplies; mutual-capacitance slider electrodes; finger-presence electrodes |
| 04 Haptic feedback | Haptic motor driver; 21 x 47 uF energy reservoir |
| 05 Programming and test | DA14531 SWD programmer; SAM L10 SWD programmer; 1.8 V and 1.1 V test pads |

Each component belongs to a native `schematicsheet` through `schSheetName` and a native `schematicsection` through `schSectionName`. Titles use native `schematictext` at explicit positions so they remain clear of routed labels. Section dividers, schematic wires, net labels and PCB routing are rendered by tscircuit.

Signals crossing section boundaries use named net labels. Matching labels refer to the same electrical net across sheets. Power and ground labels and local wiring use the native schematic router. The electrode symbols represent fabricated copper features; the motor, battery and charging coil connect through solder pads and are external assemblies.

`source-data/schematic-layout.json` holds the editable page assignments and schematic coordinates. Run `python scripts/generate-board.py` after editing that file, then build and run schematic placement checks. This generator preserves the explicit PCB positions and saved native copper paths.

`bun scripts/render-schematic.ts` exports every native sheet to SVG and PNG under `dist/index/schematic-sheets/`. The full circuit JSON retains all five sheets for the tscircuit viewer.

The revision comparison checks physical PCB geometry independently of generated record IDs, route traversal direction and record order. It separately compares deduplicated source pin-to-net connectivity. The comparison result is included in `validation-logs/schematic-revision.log`.