astra/am3352-sbc

A 4-layer AM3352 single-board computer with 128‑MiB DDR3, PMIC power regulation, USB‑C 5‑V PD input, dual USB host ports, HDMI output with ESD protection, microSD/UART/JTAG interfaces, addressable RGB indicators, and a PWM-driven buzzer.

Version
0.1.19
License
unset
Stars
0

design/timing-constraints.tsx

import { Fragment } from "react";
import { DDR_RULES, ddrTimingGroups, ddrPairs } from "./ddr-rules";

export function TimingConstraints() {
  return (
    <>
      {ddrTimingGroups.map((group) => (
        <Fragment key={group.name}>
        <bus
          name={group.name}
          connections={group.signals}
          maxLengthSkew={group.maxLengthSkew}
          pcbAllowedLayers={[...DDR_RULES.signalLayers]}
          targetImpedance={DDR_RULES.singleEndedImpedanceOhm}
        />
        </Fragment>
      ))}
      {ddrPairs.map((pair) => (
        <Fragment key={pair.name}>
        <differentialpair
          name={pair.name}
          positiveConnection={pair.signals[0]}
          negativeConnection={pair.signals[1]}
          maxLengthSkew={DDR_RULES.pairSkewMm}
          targetDifferentialImpedance={DDR_RULES.differentialImpedanceOhm}
          pcbTraceGap={DDR_RULES.provisionalPairGapMm}
        />
        </Fragment>
      ))}
      {/* RESET# is not in TI Table 7-67's clocked ADDR_CTRL class. */}
      <bus
        name="DDR_RESET_LAYER"
        connections={["DDR_RESETn_SIGNAL"]}
        pcbAllowedLayers={[...DDR_RULES.signalLayers]}
      />
    </>
  );
}