astra/am3352-sbc

design/routing-nets.tsx

import { Fragment } from "react"
import { phaseForNet } from "./nets"

/** Explicit named-net phase ownership; direct signal traces declare their own phases. */
const routedNets = [
  "A3V3",
  "AUX_5V",
  "AUX_5V_FUSED",
  "AUX_5V_PROTECTED",
  "BUZZ_DRAIN",
  "BUZZ_GATE",
  "BUZZ_PWM",
  "CAP_VBB_MPU",
  "CAP_VDD_RTC",
  "CAP_VDD_SRAM_CORE",
  "CAP_VDD_SRAM_MPU",
  "DDR_1V5",
  "DDR_RESETn",
  "DDR_VREF",
  "DDR_VTP",
  "DDR_ZQ",
  "EMU0",
  "EMU1",
  "GND",
  "HDMI_5V",
  "HDMI_ESD_BYP",
  "HDMI_HPD",
  "HDMI_HPD_5V",
  "HDMI_PVDD",
  "HDMI_SCL",
  "HDMI_SDA",
  "HDMI_TFADJ",
  "HDMI_TVDD",
  "I2C0_SCL",
  "I2C0_SDA",
  "LCD_DATA0",
  "LCD_DATA1",
  "LCD_DATA10",
  "LCD_DATA11",
  "LCD_DATA12",
  "LCD_DATA13",
  "LCD_DATA14",
  "LCD_DATA15",
  "LCD_DATA2",
  "LCD_DATA3",
  "LCD_DATA4",
  "LCD_DATA5",
  "LCD_DATA6",
  "LCD_DATA7",
  "LCD_DATA8",
  "LCD_DATA9",
  "MMC0_CLK",
  "MMC0_CMD",
  "MMC0_DAT0",
  "MMC0_DAT1",
  "MMC0_DAT2",
  "MMC0_DAT3",
  "PD_CC1",
  "PD_CC2",
  "PD_GATE",
  "PD_PGn",
  "PD_SENSE",
  "PD_VBUS",
  "PD_VDD",
  "PMIC_BYPASS",
  "PMIC_INT_LDO",
  "PMIC_PB",
  "PMIC_POWER_EN",
  "PMIC_TS",
  "PWRONRSTn",
  "RGB_BUFFERED",
  "RGB_CHAIN",
  "RGB_DIN",
  "ROUTED_LCD_AC_BIAS_EN",
  "ROUTED_LCD_HSYNC",
  "ROUTED_LCD_PCLK",
  "ROUTED_LCD_VSYNC",
  "RTC_1V8",
  "RTC_RESETn",
  "RTC_XTALIN",
  "RTC_XTALOUT",
  "SD_CD",
  "SPI0_D0",
  "SW1",
  "SW2",
  "SW3",
  "SYS_5V",
  "TCK",
  "TDI",
  "TDO",
  "TMS",
  "TRSTn",
  "UART0_RXD",
  "UART0_RXD_CABLE",
  "UART0_RXD_DEBUG",
  "UART0_TXD",
  "UART0_TXD_CABLE",
  "UART0_TXD_DEBUG",
  "USB0_DRVVBUS",
  "USB0_OCn",
  "USB0_VBUS",
  "USB1_DRVVBUS",
  "USB1_OCn",
  "USB1_VBUS",
  "USB_PD_SWITCHED",
  "V1V8",
  "V3V3",
  "VDD_CORE",
  "VDD_MPU",
  "VIN_5V",
  "WARMRSTn",
  "XTALIN",
  "XTALOUT"
] as const

export function RoutingNets() {
  return <>{routedNets.map(name => <Fragment key={name}><net name={name} routingPhaseIndex={phaseForNet(name)} /></Fragment>)}</>
}