astra/am3352-sbc

README.md

# AM3352 SBC — engineering checkpoint 0.1.19

**Routing remains incomplete. This board is not DDR compliant or ready for fabrication.**

The board has 750 native traces, 11 unconnected-port errors and 21 physically disconnected nets. The preceding published checkpoint had 748 traces and 13 unconnected-port errors. There are no dangling, missing-trace or other native trace errors.

RTC_RESETn and MMC0_DAT1 now connect end to end. The A5 ground via moves to (-8.35,-3.15) through a 1.644 mm top escape. A small inner2 V1V8 detour clears the MMC0_DAT1 barrel at (-1.65,4.5). The MMC route uses 0.10 mm copper through the crowded area and needs final SD-interface impedance/SI review. Temporary duplicate escape vias were removed. Native clearance, all ten supply rails, independent geometry/reference, replay and saved DDR/USB/HDMI checks pass.

TRSTn now connects end to end. The A9 ground via moves to (-7.4,-0.4), opening a short top escape path. A 1.62 mm inner2 section in the new TRSTn route keeps the bottom ground pour connected; the temporary narrow ground stitch was removed. All ten supply networks remain physically connected. Native clearance, independent copper/reference, replay, clock/switching and saved DDR/pair preservation audits pass. The published native checker still omits 14 disconnected LCD branches; checks PR #382 fixes that undercount. The physical audit is the completion metric.

EMU0 now connects through a 0.472 mm top escape and existing same-net through-via. C_U1_E12 and C_U1_F12 use standard 0201 footprints; C_U1_E14 uses 0201 at (-5.81,3.3), rotated 315 degrees in the bottom component frame. Local V3V3 and TMS segments avoid the new via site. The router can explicitly reuse existing same-net barrels on the exact routing grid (REUSE_OWN_VIAS=1). On the same 0.05 mm grid, the regression remains disconnected without reuse and connects with it. Duplicate escape copper was removed, and the feeder ends at an existing remote via without drilling it again. Native and independent audits pass; there are no duplicate via sites. Two acceptance regression tests cover duplicate barrels and unexpected native errors. The new route still needs final debug-interface SI review.

TMS and DDR_VTP now reach the processor through short top escapes after C_U1_E11 and C_U1_H11 were moved to standard 0201 footprints. The obsolete E11 branch was removed; a replacement bottom feed restores continuity to 3V3 through an existing via. All ten supply rails, native clearance, reference preservation, replay and saved DDR/USB/HDMI geometry pass. The new feed needs final decoupling-loop review. The checkpoint validator now explicitly rejects every native error except remaining unconnected ports.

USB0_DRVVBUS is connected through a 1.322 mm top escape after moving C_U1_G14 to a standard 0201 footprint and retaining a verified 3V3 feed. USB1 overcurrent is connected using the unused outer-row V17/GPIO1_27 input. RGB serial data now reaches B17/SPI0_D0; configure Linux McSPI with `ti,pindir-d0-out-d1-in` to drive D0 as MOSI. The feeder reaches the pad directly, so its temporary escape and via were removed. Firmware pinmux requirements and primary sources are recorded in `design/PINMUX.md` and `design/gpio-assignments.json`. These pin assignments and all saved DDR/USB/HDMI copper pass fresh native and independent incremental audits.

DDR_VREF now reaches the processor through a 0.461 mm top escape and an inner carrier. C_U1_G6 uses a standard 0201 footprint, moved and rotated while retaining its old core-supply feed junction. Native copper, all ten supply nets and reference preservation pass. R_VREF_L is now on the bottom at (-12.7,-25.5), joining the existing VREF barrel through a short bottom trace and ground through its existing ground via. DDR_VREF is physically connected across the CPU, RAM, divider and capacitor. VREF bypass placement, trace width and final part qualification remain open. This is an incremental connectivity improvement, not complete VREF or DDR signoff.

I2C0_SCL now reaches the CPU through a 0.472 mm top escape and inner carriers. C_U1_F12 was moved 0.894 mm and rotated 90 degrees; its new 1.971 mm bottom feed joins an existing MPU through-via. The previous MPU branches retain their copper and are represented as one continuous path starting at C_U1_J13. All supply and reference checks pass. I2C0_SDA, UART0_RXD and HDMI_HPD are also connected. C_U1_E13 was moved and given a replacement 3V3 feed to clear the I2C data escape; the escape is 0.461 mm on top. The two low-speed UART/hot-plug signals use longer top paths around BGA congestion before entering inner carriers. Feeders joined the top escape centerlines, so unused temporary via tails were trimmed and the complete paths were rebuilt and audited.

All ten audited supply networks remain physically connected: GND, DDR_1V5, V3V3, V1V8, VDD_CORE, VDD_MPU, A3V3, RTC_1V8, VIN_5V and SYS_5V. Top 3V3 and DDR 1V5 occupy separate regions with about 0.30 mm clearance; bottom GND is connected. These checks do not establish current capacity or power integrity.

Both crystal circuits remain on top without vias and meet the 10 mm project limit. PMIC SW1/SW2/SW3 remain on top without vias, with centerline lengths 2.153, 2.667 and 1.829 mm. Their switching-loop and thermal review remains open. The existing widened VIN_5V feed is preserved; its copper-only resistance estimate excludes vias, switches, connectors and temperature.

All 47 saved DDR paths and 24 USB/HDMI paths are preserved. Independent incremental clearance, native connectivity, supply, clock, switching-node, replay and reference-preservation audits pass. No additional reference-plane voids occur within 0.1 mm of saved inner-layer signal centerlines. This relative check does not certify the existing reference planes or the full TI DDR keepout region.

RAM remains at (-10,-32), rotated 270 degrees. DDR uses inner1/inner2 with short top escapes. All three complete timing buses and all three differential pairs remain configured. Strict absolute-length checks still fail: BYTE0 reaches 45.4304 mm against 42.4001 mm; BYTE1 reaches 40.0829 mm against 36.0003 mm. Existing 0.10 mm ordinary tracks and 0.12 mm pair gaps still need migration to the working 0.14 mm single-ended and 0.10 mm/0.18 mm differential geometry. Solver experiments and rejected candidates are isolated and are not published as accepted copper.

Fabrication target: JLCPCB nominal 1.6 mm four-layer controlled impedance, working stackup JLC04161H-3313. Remaining routing, strict DDR replacement, impedance confirmation, package/via flight times, SI, continuous reference planes, stitching, power capacity, decoupling and component/footprint review remain open.

Dependencies remain tscircuit 0.0.2744, core 0.0.2079, props 0.0.685, bus-lanes-solver 0.0.19 and checks 0.0.239. Dependency lock entries are preserved. Solver 0.0.21 experiments remain separate. Relevant upstream PRs: https://github.com/tscircuit/core/pull/4369, https://github.com/tscircuit/core/pull/4373, https://github.com/tscircuit/bus-lanes-solver/pull/40 and https://github.com/tscircuit/checks/pull/381.

Validation: typecheck; seven DDR constraint tests with 17 assertions; fresh native render and all incremental audits pass. Strict DDR acceptance fails as described above. `tsci build --site` produces the viewer with the expected incomplete-board exit status. Its copper/connectivity/error records match the independently audited circuit; supplier metadata may differ. `bun scripts/portable-site.ts` creates `dist/board.html`. Evidence is in `output/report.json` and accompanying audits.