astra/am3352-ram-test-blank

A 324-ball TI AM3352 ARM processor/SoC footprint with DDR, LCD, USB, Ethernet, MMC, GPMC, serial, SPI/I²C, audio, ADC, clock, power, and JTAG interfaces, plus DDR routing constraints.

Version: 0.0.2
License: unset
Stars: 0

README.md

# AM3352 RAM test — blank

Derived from https://tscircuit.com/seveibar/am3352-dev-board-4layer-dogbone.

Only U1 (AM3352BZCZ100), U3 (W631GG6MB-12), and their shared logical nets remain. Original footprints, placements, 70 × 60 mm board, four layers, 1.2 mm thickness, and clearance settings are preserved. Shared nets include the DDR signals, DDR_VREF, DDR_1V5, and GND. Removed-component branches and chip-only nets are omitted.

All physical routing, dogbone escapes, vias, copper pours, other components, mounting holes, and routing replay phases are removed. `routingDisabled` keeps the baseline unrouted on rebuild. The original DDR timing constraints are retained: two byte buses (0.635 mm maximum skew), three differential pairs (0.127 mm maximum skew), and 0.12 mm pair gap. Routing strategy will be developed after review.