astra-abse/t113-s3

Allwinner T113-S3 / JLCPCB C5197687: native saved fanout, LCD top, storage right, 127 perimeter exits, 30 decoupling capacitors, connected GND planes; clean DRC and shorts, all 29 vias connected.

Version
1.2.0
License
MIT
Stars
0

reports/verification.md

# T113-S3 fanout verification

Status: **PASS**

- JLCPCB: C5197687; imported exact footprint retained.
- Pads: 189 (129 SoC + 60 capacitor); perimeter exits: 127; internal joins: 61; pin 106 deliberately open.
- LCD: 22 signals exit top; storage: 12 signals exit right.
- Copper traces: 188, including decoupling and the AGND–EPAD connection.
- Vias: 29 unique, connected through vias; 0.45 mm pads / 0.20 mm drills.
- GND: bottom and inner1 pours; all 32 ground pads physically connected.
- Decoupling: 30 bottom-mounted 0402 capacitors.
- Core/CLI DRC: 0 errors, 0 warnings; no DRC bypasses.
- Independent copper check: 237846 pairs, 0 violations.
- Minimum measured different-net clearance: 0.114796 mm (rule: 0.10 mm).
- Gerber and PCB bitmap shorts: 0, all layers, 100 pixels/mm.
- TypeScript and regression/integration tests pass.

Artifact SHA-256: `5be1ec686fc1bb9df5b05d5befec58fa92b78ec1976394ba17a0ccb90ccd40e2`

See verification.json and individual command logs for exact versions and commands.

Scope: fanout copper and routing connectivity; this is not a complete powered SoC design or signal-integrity qualification.