abse/smart-ring-flex

validation/native-final-cleanup4.log

Building 1 file(s)...
Building index.circuit.tsx...
Generating circuit JSON...
Circuit JSON written to dist/index/circuit.json
The "Q" prefix is being used with a <chip />, try using it with a <transistor />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "Q" prefix is being used with a <chip />, try using it with a <transistor />
The "L" prefix is being used with a <chip />, try using it with an <inductor />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
Q10 has no pin with requires_power=true
Q10 has no pin with requires_ground=true
All pins on Q10 are underspecified (no pinAttributes set)
All pins on PAD_CHARGE_POS are underspecified (no pinAttributes set)
All pins on PAD_CHARGE_GND are underspecified (no pinAttributes set)
J101 has no pin with requires_power=true
J101 has no pin with requires_ground=true
J105 has no pin with requires_power=true
J105 has no pin with requires_ground=true
All pins on J105 are underspecified (no pinAttributes set)
Q106 has no pin with requires_power=true
Q106 has no pin with requires_ground=true
All pins on Q106 are underspecified (no pinAttributes set)
DOCK_FLEX_ROOT has no pin with requires_power=true
DOCK_FLEX_ROOT has no pin with requires_ground=true
All pins on DOCK_FLEX_ROOT are underspecified (no pinAttributes set)
All pins on PG301 are underspecified (no pinAttributes set)
All pins on PG302 are underspecified (no pinAttributes set)
U9 has no pin with requires_power=true
U9 has no pin with requires_ground=true
U8 has no pin with requires_power=true
LED1 has no pin with requires_power=true
LED1 has no pin with requires_ground=true
All pins on LED1 are underspecified (no pinAttributes set)
PD1 has no pin with requires_power=true
PD1 has no pin with requires_ground=true
All pins on PD1 are underspecified (no pinAttributes set)
PD2 has no pin with requires_power=true
PD2 has no pin with requires_ground=true
All pins on PD2 are underspecified (no pinAttributes set)
U_TH1 has no pin with requires_power=true
U_TH1 has no pin with requires_ground=true
All pins on U_TH1 are underspecified (no pinAttributes set)
U_TH2 has no pin with requires_power=true
U_TH2 has no pin with requires_ground=true
All pins on U_TH2 are underspecified (no pinAttributes set)
JSWD1 has no pin with requires_power=true
JSWD1 has no pin with requires_ground=true
All pins on JSWD1 are underspecified (no pinAttributes set)
PAD_CHARGE_POS has no courtyard
PAD_CHARGE_GND has no courtyard
DOCK_FLEX_ROOT has no courtyard
U_NEG is inferred to face x- from its cable insertion center because no explicit footprint insertionDirection is defined, but should face y- so the connector is accessible from the board edge. Set insertionDirection on the <footprint> to specify the actual direction in the footprint's unrotated orientation; for example, <footprint insertionDirection="from_above"> for a connector accessed from above the PCB (+Z).
JPOS is inferred to face x- from its cable insertion center because no explicit footprint insertionDirection is defined, but should face x+ so the connector is accessible from the board edge. Set insertionDirection on the <footprint> to specify the actual direction in the footprint's unrotated orientation; for example, <footprint insertionDirection="from_above"> for a connector accessed from above the PCB (+Z).
Trace [.J101 > .EH2 to .J101 > .EH1] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.CHV16 > .bottom to .CHV17 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.U101 > .OUT to .DOCK_FLEX_ROOT > .pin2] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.CHV10 > .bottom to .CHV11 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.PAD_CHARGE_GND > .GND to .R133 > .pin2] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.RCV_132 > .bottom to .RCV_133 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.PAD_CHARGE_POS > .POS to .R134 > .pin2] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.R23 > .pin1 to .R25 > .pin1] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.RCV_5 > .bottom to .RCV_10 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.U1 > .P0_14 to .U3 > .SDA] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.VSES_53 > .bottom to .VSES_54 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.R131 > .pin2 to .U1 > .SWDIO] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.SDIO > .bottom to .VSES_95 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.R130 > .pin2 to .U1 > .SWDCLK] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.SWCLK_TEST_ESCAPE_L > .bottom to .ELASTIC_SWDCLK_1002001 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.VSES_73 > .bottom to .FINAL_RESET_1 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.Q10 > .pin2 to .R25 > .pin2] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.NEAR_KEEP_JSWD1_0 > .bottom to .FINAL_CHARGE_DISABLE_1 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.NEAR_VBAT_SENSE_0 > .bottom to .NEAR_VBAT_SENSE_1 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.RXA > .bottom to .RXB > .bottom] is routed thinner than requested (requested: 0.2mm, actual: 0.1mm).
Trace [.U6 > .pin4 to .U9 > .pin1] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.VSES_14 > .bottom to .VSES_15 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.U1 > .pin46 to .VSES_24 > .top] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.VSES_24 > .bottom to .VSES_25 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.U6 > .pin5 to .R6 > .pin2] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.VSES_71 > .bottom to .VSES_72 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.U1 > .pin30 to .L1 > .pin1] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.VSES_75 > .bottom to .VSES_76 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.U2 > .pin2 to .JPOS > .pin1] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.VSES_96 > .bottom to .VSES_97 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.U1 > .pin34 to .Y1 > .pin1] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.VSES_126 > .bottom to .VSES_127 > .bottom] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
Trace [.U1 > .pin35 to .Y1 > .pin3] is routed thinner than requested (requested: 0.1mm, actual: 0.08mm).
.PAD_CHARGE_GND > .GND to .R133 > .pin2 has a 8.84 mm segment on top at 305.00°, 10.00° from the nearest allowed direction (315°). Prefer a multiple of 45° for segments longer than 5 mm (tolerance 4°).
.PAD_CHARGE_POS > .POS to .R134 > .pin2 has a 8.84 mm segment on top at 305.00°, 10.00° from the nearest allowed direction (315°). Prefer a multiple of 45° for segments longer than 5 mm (tolerance 4°).

Build complete
  Circuits  1 passed
  Output    dist

✓ Done
Build exiting with code 0: build finished successfully