abse/gameboy-advance

firmware/lcd-parallel-test/README.md

# R24 parallel LCD bring-up plan (not yet hardware validated)

This profile is for the **new 8080 PCB revision only**. Keep `../lcd-test`
unchanged as the recoverable SPI test for the existing prototype.

ILI9488 DBI Type B: IM2/IM1/IM0 = 0/1/1; DB0..DB7 = LCD FPC32..25.
D0..D7 = RP2350 GPIO15..22; WR = GPIO23; DC = GPIO25;
RESET = GPIO10; CS = ground; RD = I/O supply. Backlight remains GPIO24.
Select moves to GPIO0; audio PWM moves to GPIO1. Start remains GPIO11.
Capacitive touch is unavailable with this allocation; purchased panel is non-touch.

Set COLMOD (0x3A) to 0x55 (RGB565). Send each pixel high byte first,
then low byte. Keep DC stable and wait for the PIO FIFO **and shifter** to
finish before changing command/data mode or resetting the display.

At 480×320, 33 full frames/s needs 10,137,600 bytes/s, excluding commands.
Proposed PIO byte cycle at a 150 MHz PIO instruction clock:

```
.program lcd8080
.side_set 1
.wrap_target
    out pins, 8 side 1 [2] ; 20 ns setup
    nop         side 0 [2] ; 20 ns WR low
    nop         side 1 [3] ; 26.67 ns WR high / hold
.wrap
```

Configure OUT base15/count8, side-set base23, right shift/autopull8,
TX-only FIFO, and DMA paced by the state-machine TX DREQ. All pins must be
outputs. This gives 15 million write strobes/s, 15 MB/s, and a theoretical
48.83 full frames/s before overhead. FIFO starvation stalls at OUT with WR
high. Use native C/C++ with the Pico SDK, never MicroPython here.

ILI9488 specification §17.4.1 requires write cycle ≥30 ns, WR high/low
≥15 ns, data setup/hold ≥10 ns. The proposed schedule meets those values at
the controller before PCB/cable skew and edge quality are measured.

Bench acceptance: check actual module mode/pin straps; start slow; verify
all eight walking data bits, RGB565 color bars, orientation and full window;
then increase write clock and scope WR/data at the FPC. Measure **completed**
full-frame DMA transfers for ≥60 s, looking for tearing, missing pixels,
color errors and supply disturbance. Do not advertise measured33FPS until
that test succeeds while the intended application also renders/audio runs.

For the original RGB666 color depth (262,144 colors), parallel DBI also allows
three writes/pixel with COLMOD0x66. 33fps then needs15,206,400bytes/s.
An optional8-cycle byte schedule at150MHz (`out side1 [1]`,
`nop side0 [2]`, `nop side1 [2]`) gives18.75MB/s and a theoretical40.69fps.
Data setup is13.33ns; WR low/high are20ns/33.33ns. This tighter timing
profile also needs oscilloscope and sustained full-frame validation; start
with the conservative15MHz RGB565 profile above.