abse/boostxl-tmp107

docs/design-verification.md

# Design verification record

## Electrical cross-check against TI MHR035 Rev A

| TI schematic item | Implemented result |
|---|---|
| J1/J2 `SSQ-110-03-T-D` | Exact MPN and JLCPCB C5379997; both sockets mounted on the bottom so the female bodies point below the BoosterPack. |
| U1 `SN74LVC1G07DBVR` | Exact MPN/JLCPCB C7829; A driven from UCA0TXD, Y feeds J3 mode 1, VCC on 3.3 V, GND grounded, NC unconnected. |
| R1 3.3 kΩ | Pull-up from 3.3 V to U1 open-drain output. |
| R2 10 kΩ | Series/current-limited UART mode between UCA0TXD and J3. |
| J3 modes | Pins 1-2 select open-drain buffer, 3-4 select resistor path, and 5-6 select direct drive. Each right-side pin joins the TMP107 IO1 bus. |
| U2/U3/U4 `TMP107BIDR` | Exact MPN/JLCPCB C2870479; IO2 of each sensor feeds IO1 of the next node. |
| C1-C4 0.1 µF | One 100 nF bypass capacitor per active IC. |
| ALERT1/ALERT2 | U2 alert outputs route to the LaunchPad interface; coupon-node alert outputs are intentionally unconnected as shown by TI. |

## Mechanical reconstruction

- Board outline: 53.34 mm x 40.64 mm.
- Two 2x10 BoosterPack sockets use the standard 2.54 mm grid and are bottom-mounted.
- J3 is a vertical, top-entry 2x3 header.
- U3 and U4 occupy two lower breakaway coupons with input/output power, data, and ground holes. Their SOIC pins face the upper and lower coupon edges, matching the TI assembly photograph.
- Ten horizontal routed slots form the main break line; two groups of three vertical routed slots bound U3 on the left and divide U3 from U4 while retaining narrow tabs.

Mechanical values are image/grid-derived because TI does not currently publish the original CAD/Gerber archive on the product page. Confirm LaunchPad enclosure clearance, coupon break strength, and hole locations on a 1:1 print before fabrication.

## Automated release gate

`bun run release-check` requires:

- successful TypeScript and tscircuit build;
- zero `*error*` elements in generated circuit JSON;
- exact board/via constraints and expected component identities;
- all non-passive populated parts tied to JLCPCB supplier IDs;
- both female sockets on the bottom layer;
- routed traces, vias, bottom copper pour, and sixteen breakaway slots;
- a successful local `tsci check shorts` result.

After those checks, fabricate a small prototype batch and bench-test 3.3 V current, UART communication in all three J3 modes, ALERT outputs, daisy-chain enumeration, temperature readings, and breakaway-node continuity before ordering production quantity.