ShiboSoftwareDev/t113-s3-linux-computer-p9

The code defines a PCB subcircuit for a buck converter module featuring a TMI3112H IC, FTC252010S power switch, and associated passive components like capacitors and resistors for voltage regulation and feedback control.

Version
0.1.4
License
unset
Stars
0

subcircuits/power-input.tsx

import { BuckRail } from "../components/buck-rail"
import { part } from "../components/standard-passives"
import { UsbPowerFrontend } from "./usb-power-frontend"

const SECTION = "POWER_INPUT"

export const PowerInputSubcircuit = ({ exposeToParent = true }: { exposeToParent?: boolean }) => (
  <subcircuit
    name="POWER_INPUT"
    width="66mm"
    height="38mm"
    autorouter="default"
    autorouterVersion="beta_pipeline9"
    autorouterEffortLevel="10x"
    defaultTraceWidth="0.15mm"
    exposeNets={exposeToParent}
    schAutoLayoutEnabled
    schTraceAutoLabelEnabled
  >
    <net name="VBUS_RAW_5V" isPowerNet nominalTraceWidth="0.8mm" />
    <net name="VBUS_5V" isPowerNet nominalTraceWidth="0.8mm" />
    <net name="VDD_3V3" isPowerNet nominalTraceWidth="0.6mm" />
    <net name="VCORE_0V9" isPowerNet nominalTraceWidth="0.6mm" />
    <net name="USB0_DP" />
    <net name="USB0_DM" />
    <net name="GND" isGroundNet nominalTraceWidth="0.5mm" />

    <UsbPowerFrontend />
    <BuckRail id="RAIL_3V3" x={-3} y={3} outputNet="VDD_3V3" outputLabel="3V3 / 2A"
      feedbackTop={part.r453k} enableFrom="VBUS_5V" sectionName={SECTION} />
    <BuckRail id="RAIL_0V9" x={13} y={3} outputNet="VCORE_0V9" outputLabel="0V9 CORE / 2A"
      feedbackTop={part.r49k9} enableFrom="VDD_3V3" delayed sectionName={SECTION} />

    <silkscreentext text="POWER: 5V -> 3V3 -> delayed 0V9" pcbX={7} pcbY={12} fontSize="0.65mm" />
  </subcircuit>
)